LTC2170IUKG-12#PBF Linear Technology, LTC2170IUKG-12#PBF Datasheet - Page 23

• Manufacturer Part Number: LTC2170IUKG-12#PBF
• Description: IC ADC 12BIT SER/PAR 25M 52-QFN
• Manufacturer: Linear Technology

Specifications of LTC2170IUKG-12#PBF

• Number Of Bits: 12
• Sampling Rate (per Second): 25M
• Data Interface: Serial, Parallel
• Number Of Converters: 4
• Power Dissipation (max): 238mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
By default the outputs are standard LVDS levels: a 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV
isolated from the A/D core power and ground.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current can
be adjusted by control register A2 in serial programming
mode. Available current levels are 1.75mA, 2.1mA, 2.5mA,
3mA, 3.5mA, 4mA and 4.5mA. In parallel programming
mode the SCK pin can select either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any refl ections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing. In
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2172-12. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2171-12) or 25MHz (LTC2170-12).
SERIALIZATION MODE
2-Lane
2-Lane
2-Lane
1-Lane
1-Lane
1-Lane
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
DD
and OGND which are
MAXIMUM SAMPLING
FREQUENCY , f
62.5
65
65
65
65
65
S
(MHz)
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
In addition to the 12 data bits (D11 - D0), two additional
bits (D
serialization modes. These extra bits are to ensure com-
plete software compatibility with the 14-bit versions of
these A/Ds. During normal operation when the analog
inputs are not overranged, D
When the analog inputs are overranged positive, D
D
negative, D
be controlled by the digital output test pattern. See the
Timing Diagrams section for more information.
Table 2. Output Codes vs Input Voltage
A
(2V RANGE)
>+1.000000V
+0.999512V
+0.999024V
+0.000488V
–0.000488V
–0.000976V
–0.999512V
–1.000000V
≤–1.000000V
0.000000V
IN
DCO FREQUENCY
Y
+
become logic 1. When the analog inputs are overranged
– A
3.5 • f
IN
4 • f
3 • f
8 • f
7 • f
6 • f
X
LTC2171-12/LTC2170-12
–
and D
S
S
S
S
S
S
X
and D
(OFFSET BINARY)
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
Y
) are sent out in the 14-bit and 16-bit
D11-D0
Y
become logic 0. D
FR FREQUENCY
0.5 • f
f
f
f
f
f
S
S
S
S
S
X
S
(2’s COMPLEMENT)
and D
LTC2172-12/
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
D11-D0
Y
are always logic 0.
X
SERIAL DATA RATE
and D
16 • f
14 • f
12 • f
8 • f
7 • f
6 • f
Y
can also
S
S
S
S
S
S
D
23
X
21721012f
11
00
00
00
00
00
00
00
00
00
, D
X
and
Y