LTC1744IFW#TR Linear Technology, LTC1744IFW#TR Datasheet - Page 18

• Manufacturer Part Number: LTC1744IFW#TR
• Description: IC ADC 14BIT 50MSPS 48-TSSOP
• Manufacturer: Linear Technology

Specifications of LTC1744IFW#TR

• Number Of Bits: 14
• Sampling Rate (per Second): 50M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.5W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1744IFWTR

APPLICATIO S I FOR ATIO
LTC1744
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50 to external
circuitry and may eliminate the need for external damping
resistors.
Output Loading
As with all high speed/high resolution converters the
digital output loading can affect the performance. The
digital outputs of the LTC1744 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 43 on chip.
18
U
U
LATCH
FROM
DATA
W
Figure 9. Equivalent Circuit for a Digital Output Buffer
OE
DD
and OGND, iso-
PREDRIVER
LOGIC
V
DD
U
V
Lower OV
from the digital outputs.
Format
The LTC1744 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MSBINV pin; high selects offset binary.
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. When OF outputs a logic high
the converter is either overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal ENCODE. Data
will be updated just after CLKOUT falls and can be latched
on the rising edge of CLKOUT.
DD
DD
OV
DD
voltages will also help reduce interference
LTC1744
43
1744 F09
OV
OGND
DD
0.1 F
0.5V TO
V
TYPICAL
DATA
OUTPUT
DD
1744f