AD7738BRU Analog Devices Inc, AD7738BRU Datasheet - Page 13

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AD7738BRU

Manufacturer Part Number
AD7738BRU
Description
IC ADC 24BIT 8-CH 28-TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7738BRU

Rohs Status
RoHS non-compliant
Number Of Bits
24
Sampling Rate (per Second)
15.4k
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
100mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP (0.173", 4.40mm Width)
For Use With
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REGISTER DESCRIPTION
The AD7738 is configurable through a series of registers. Some of them configure and control general AD7738 features, others are
specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the Communication
register, i.e., any communication to the AD7738 must start with a write to the Communication register, specifying which register
will be subsequently read or written.
Communications Register
8 Bits, Write-Only Register, Address 00h
All communications to the part must start with a write operation to the Communications register. The data written to the Commu-
nications register determines whether the subsequent operation will be a read or write and to which register this operation will be
directly placed. The digital interface defaults to expect write operation to the Communication register after power on, after reset, or
after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset
by writing at least 32 serial clock cycles with DIN high and CS low (Note that all of the parts including modulator, filter, interface
and all registers are reset in this case). Remember to keep DIN low while reading 32 or more bits either in Continuous Read mode or
with the DUMP bit and “24/16” bit in the Mode register set.
Bit
Mnemonic
Bit
7
6
5–0
REV. 0
Mnemonic
0
R/W
Address
Bit 7
0
Description
This bit must be zero for proper operation.
A zero in this bit indicates that the next operation will be a write to a specified register.
A one in this bit indicates that the next operation will be a read from a specified register.
Address specifying to which register the read or write operation will be directed.
For channel specific registers the three LSBs, i.e., Bit 2, Bit 1, and Bit 0, specify the channel number.
When the subsequent operation writes to the Mode register, then the three LSBs specify the channel
selected for operation determined by the Mode register value. See Table X.
(The analog input’s configuration depends on the COM1, COM0 bits in the Channel Setup register.)
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Bit 6
R/W
Bit 0
0
1
0
1
0
1
0
1
Bit 5
Channel
0
1
2
3
4
5
6
7
–13–
Table X.
Bit 4
Single Input
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Bit 3
6-Bit Register Address
Differential Input
AIN0–AIN1
AIN2–AIN3
AIN4–AIN5
AIN6–AIN7
AIN0–AIN1
AIN2–AIN3
AIN4–AIN5
AIN6–AIN7
Bit 2
Bit 1
AD7738
Bit 0

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