AD7738BRU Analog Devices Inc, AD7738BRU Datasheet - Page 24

• Manufacturer Part Number: AD7738BRU
• Description: IC ADC 24BIT 8-CH 28-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7738BRU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 15.4k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• For Use With: EVAL-AD7738EBZ - BOARD EVAL FOR AD7738

AD7738
Multiplexer, Conversion, and Data Output Timing
The specified “Conversion Time” includes one or two “Settling”
and “Sampling” periods and a “Scaling” time.
With chopping enabled (Figure 14), a conversion cycle starts
with a “Settling” time of 43 or 44 MCLK cycles (~7 µs with
6.144 MHz MCLK) to allow the circuits following the multiplexer
to settle. Then the sigma-delta modulator samples the analog
signals, and the digital filter processes the digital data stream.
The “Sampling” time depends on FW, i.e., on the Channel
Conversion Time register contents. After another “Settling” of
42 MCLK cycles (~6.8 µs), the “Sampling” time is repeated
with a reversed (chopped) analog input signal. Then, during the
“Scaling” time of 163 MCLK cycles (~26.5 µs), the two results
from the digital filter are averaged, scaled using the Calibration
registers, and written into the Channel Data register.
With chopping disabled (Figure 15), there is only one “Sampling”
time preceded by a “Settling” time of 43 or 44 MCLK cycles
and followed by a “Scaling” time of 163 MCLK cycles.
The RDY pin goes high during the “Scaling time” regardless of
its previous state. The relevant RDY bit is set in the ADC Sta-
tus register, and in the Channel Status register the RDY pin
goes low when the Channel Data register is updated and the
Figure 15. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled
Figure 14. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled
AIN(– )
AIN(+)
MULTIPLEXER
CHOP
MULTIPLEXER
MUXOUT
RDY
MULTIPLEXER
Figure 13. Channel Signal Chain Diagram with Chopping Enabled
-CHANNEL 0
ADCIN
BUFFER
RDY
f
MCLK
SETTLING
/2
+CHANNEL 0
TIME
MODULATOR
+CHANNEL 1
f
MCLK
SETTLING
-
SAMPLING
TIME
TIME
/2
–24–
CONVERSION TIME
CONVERSION TIME
DIGITAL
SAMPLING
FILTER
SETTLING
+CHANNEL 1
TIME
TIME
channel conversion cycle is finished. If in Continuous Conversion
mode, the part will automatically continue with a conversion
cycle on the next enabled channel.
Note, that every channel can be configured independently for
conversion time and chopping mode. The overall cycle and effec-
tive per channel data rate depends on all enabled channel settings.
Frequency Response
The sigma-delta modulator runs at 1/2 of MCLK frequency,
which is effectively the sampling frequency. Therefore, the
Nyquist frequency is 1/4 of the MCLK frequency. The digital
filter, in association with the modulator, features frequency
response of a first order low-pass filter. The –3 dB point is close
to the frequency of 1/Channel Conversion Time. The roll-off is
–20 dB/dec up to the Nyquist frequency. If chopping is enabled,
the input signal is resampled by chopping. Therefore, the over-
all frequency response features notches close to the frequency of
1/Channel Conversion Time. The top envelope is again the
ADC response of –20 dB/dec.
The typical frequency response plots are in Figure 16. The plots
are normalized to 1/Channel Conversion Time.
CHOP
SAMPLING
-CHANNEL 1
+
-
SCALING
TIME
TIME
(CALIBRATIONS)
ARITHMETIC
SCALING
+CHANNEL 2
SCALING
TIME
INTERFACE
DIGITAL
+CHANNEL 2
OUTPUT DATA
AT THE SELECTED
DATA RATE
REV. 0