MAX105ECS+ Maxim Integrated Products, MAX105ECS+ Datasheet - Page 13

• Manufacturer Part Number: MAX105ECS+
• Description: IC ADC 6BIT 800MSPS DL 80TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX105ECS+

• Number Of Bits: 6
• Sampling Rate (per Second): 800M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 2.6W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Number Of Adc Inputs: 2
• Conversion Rate: 800 MSPs
• Resolution: 6 bit
• Snr: 37 dB
• Voltage Reference: 2.5 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Power Dissipation: 3.5 W
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Digital Output Codes Corresponding to a DC-Coupled Single-Ended Analog
Input
Table 2. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input
MAX105 LVDS-outputs provide a typical ±270mV volt-
age swing around a common mode voltage of roughly
+1.2V, and must be differentially terminated at the far
end of each transmission line pair (true and comple-
mentary) with 100Ω.
A single output pair (DOR+, DOR-) is provided to flag
an out-of-range condition, if either the I or Q channel is
out-of-range, where out-of-range is above +FS or below
-FS. It features the same latency as the ADCs output
data and is demultiplexed in a similar fashion. With a
800MHz system clock, DOR+ and DOR- are clocked at
up to 400MHz.
The MAX105 is designed to work at full-speed for both
single-ended and differential analog inputs without sig-
nificant degradation in its dynamic performance. Both
input channels I (INI+, INI-) and Q (INQ+, INQ-) have
2kΩ impedance and allow for AC- and DC-coupled
input signals. In a typical DC-coupled single-ended
configuration
the analog input amplifier stages at the in-phase-input
pins INI+/INQ+, while the inverted phase input INI-
/INQ- pins are AC-coupled to AGNDI/AGNDQ. Single-
+200mV - 0.25LSB + V
-200mV + 0.25LSB + V
+400mV - 0.5LSB + V
-400mV + 0.5LSB + V
IN-PHASE INPUTS
IN-PHASE INPUTS
>+200mV + V
> +400mV + V
<-200mV + V
< -400mV + V
(INI+, INQ+)
(INI+, INQ+)
0V + V
0V + V
(Table 1), the analog input signals enter
Applications Information
REF
REF
______________________________________________________________________________________
REF
REF
REF
REF
Single-Ended Analog Inputs
Dual, 6-Bit, 800Msps ADC with On-Chip,
REF
REF
REF
REF
Out-Of-Range Operation
-200mV + 0.25LSB + V
+200mV - 0.25LSB + V
AC – Coupled to AGND_
AC – Coupled to AGND_
AC – Coupled to AGND_
AC – Coupled to AGND_
AC – Coupled to AGND_
INVERTED INPUTS
INVERTED INPUTS
>+200mV + V
<-200mV + V
(INI-, INQ-)
0V + V
(INI-, INQ-)
REF
REF
REF
REF
REF
Wideband Input Amplifier
ended operation allows for an input amplitude of
800mV
To obtain +FS digital outputs with differential input drive
(Table 2), 400mV must be applied between INI+ (INQ+)
and INI- (INQ-). Midscale digital output codes occur
when there is no voltage difference between INI+
(INQ+) and INI- (INQ-). For a -FS digital output code
both in-phase (INI+, INQ+) and inverted input (INI-,
INQ-) must see -400mV.
An RF balun (Figure 3) provides an excellent solution to
convert a single-ended signal to a fully differential sig-
nal, required by the MAX105 for optimum performance.
At higher frequencies, the MAX105 provides better
SFDR and THD with fully differential input signals over
single-ended input signals. In differential input mode,
even-order harmonics are suppressed and each input
requires only half the signal-swing compared to single-
ended mode.
The MAX105 features clock inputs designed for either
single-ended or differential operation with very flexible
input drive requirements. The clock inputs (AC- or DC-
coupled) provide a 5kΩ input impedance to AV
OUT-OF-RANGE BIT
OUT-OF-RANGE BIT
(DOR+, DOR-)
(DOR+, DOR-)
p-p
, centered around V
1
0
0
0
1
1
0
0
0
1
Single-Ended to Differential
Differential Analog Inputs
Conversion Using a Balun
REF
.
OUTPUT CODE
OUTPUT CODE
000000/111111
000000/111111
011111
011111
100000
100000
011111
011111
100000
100000
Clock Input
CC
13
/2