AD7879ACPZ-RL Analog Devices Inc, AD7879ACPZ-RL Datasheet - Page 31

• Manufacturer Part Number: AD7879ACPZ-RL
• Description: IC ADC 12BIT CTLR TOUCH 16LFCSP
• Manufacturer: Analog Devices Inc
• Type: Touch Screen Controller: 4-Wire Resistiver

Specifications of AD7879ACPZ-RL

• Resolution (bits): 12 b
• Data Interface: I²C
• Package / Case: 16-LFCSP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.6 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Voltage Supply Source: Single Supply
• Sampling Rate (per Second): 105k
• Sampling Rate: 105kSPS
• Supply Voltage Range - Analog: 1.6V To 3.6V
• Supply Current: 480µA
• Digital Ic Case Style: CSP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SCL
DOUT
Reading Data
A read transaction begins when the master writes the command
word to the AD7879 with the read/write bit set to 1. The master
then supplies 16 clock pulses per data-word to be read, and the
AD7879 clocks out data from the addressed register on the SDA
line. The first data-word is clocked out on the first falling edge
of SCL following the command word, as shown in Figure 40.
DIN
CS
SCL
DIN
CS
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
15
NOTES
1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE DOUT PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
1
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
XXX
CW
ENABLE WORD
CW
15
14
t
2
1
2
t
1
CW
XXX
ENABLE WORD
CW
13
14
3
2
t
CW
12
3
XXX
CW
13
4
3
CW
11
5
CW
XXX
12
R/W
CW
4
10
16-BIT COMMAND WORD
6
XXX
CW
11
CW
9
5
7
R/W
t
XXX
CW
4
CW
10
8
16-BIT COMMAND WORD
6
8
STARTING REGISTER ADDRESS
CW
XXX
CW
7
9
9
7
CW
6
XXX
CW
10
8
8
Figure 40. Single Register Read Back SPI Timing
Figure 39. Sequential Register Write SPI Timing
CW
5
XXX
CW
11
7
t
5
9
CW
4
REGISTER ADDRESS
12
XXX
CW
6
10
CW
3
Rev. 0 | Page 31 of 36
13
XXX
CW
5
CW
11
2
14
XXX
CW
CW
4
`
1
12
15
XXX
CW
CW
0
3
The AD7879 continues to clock out data on the DOUT line
provided the master continues to supply the clock signal on
SCL. The read transaction finishes when the master takes
CS high. If the AD7879 address pointer reaches its maximum
value, the AD7879 repeatedly clocks out data from the
addressed register. The address pointer does not wrap around.
16
13
D15
XXX
CW
17
2
14
DATA FOR STARTING
REGISTER ADDRESS
D14
18
XXX
CW
1
15
XXX
CW
0
16
D15
X
D1
17
31
t
6
D14
D0
X
32
18
D15
16-BIT READBACK DATA
D13
X
33
19
D14
REGISTER ADDRESS
34
DATA FOR NEXT
D2
X
30
D1
47
D1
X
D0
t
8
31
AD7879
48
t
7
D15
D0
X
49
32
XXX