AD9277BSVZ Analog Devices Inc, AD9277BSVZ Datasheet - Page 34

• Manufacturer Part Number: AD9277BSVZ
• Description: IC ADC 14BIT LNA/VGA/AAF 100TQFP
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9277BSVZ

• Resolution (bits): 14 b
• Data Interface: Serial, SPI™
• Sampling Rate (per Second): 10M ~ 50M
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Sampling Rate: 50MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Supply Current: 365mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9277
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 68).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9277.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the original
clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
Power Dissipation and Power-Down Mode
As shown in Figure 69 and Figure 70, the power dissipated by
the AD9277 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and the bias current of the
LVDS output drivers.
SNR Degradation = 20 × log10(1/2 × π × f
130
120
100
110
90
80
70
60
50
40
30
1
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 68. Ideal SNR vs. Input Frequency and Jitter
ANALOG INPUT FREQUENCY (MHz)
10
J
) can be calculated as follows:
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
100
A
× t
16 BITS
14 BITS
12 BITS
J
)
1000
Rev. 0 | Page 34 of 48
A
)
The AD9277 features scalable LNA bias currents (see Table 18,
Register 0x12). The default LNA bias current settings are high.
Figure 71 shows the typical reduction of AVDD2 current with
each bias setting. It is also recommended that the LNA offset be
adjusted using Register 0x10 (see Table 18) when the LNA bias
setting is low.
Figure 71. AVDD2 Current at Different LNA Bias Settings, f
MID-HIGH
MID-LOW
300
250
200
150
100
220
215
210
205
200
195
190
185
180
175
170
HIGH
LOW
50
0
Figure 70. Power per Channel vs. f
0
0
Figure 69. Supply Current vs. f
0
50
10
10
SAMPLING FREQUENCY (MSPS)
SAMPLING FREQUENCY (MSPS)
100
TOTAL AVDD2 CURRENT (mA)
20
20
150
I
I
AVDD1
DRVDD
200
30
30
SAMPLE
SAMPLE
250
for f
for f
40
IN
40
= 5 MHz
IN
300
= 5 MHz
SAMPLE
350
50
50
= 50 MSPS
400