ISL22313UFU10Z Intersil, ISL22313UFU10Z Datasheet - Page 12

• Manufacturer Part Number: ISL22313UFU10Z
• Description: IC POT DGTL 256TP LN LP 10-MSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22313UFU10Z

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.25 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The WIP bit (ACR[5]) is a read-only bit. It indicates that non-
volatile write operation is in progress. It is impossible to write
to the WR or ACR while WIP bit is 1.
I
The ISL22313 supports an I
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22313
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 16). On power-up of the ISL22313, the SDA pin is in
the input mode.
2
C Serial Interface
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
SDA
SCL
2
2
12
C bidirectional bus oriented
C interface is conducted by
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
RH
RW
RL
START
STABLE
DATA
ISL22313
CHANGE
DATA
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22313 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 16). A START condition is ignored during the power-
up of the device.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK (Acknowledge) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
The ISL22313 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22313 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 10100 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is the Read/Write bit. Its value is
“1” for a Read operation and “0” for a Write operation (see
Table 3).
(MSB)
1
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
STABLE
DATA
LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY
TABLE 3. IDENTIFICATION BYTE FORMAT
0
1
0
STOP
0
A1
A0
July 17, 2007
FN6421.0
(LSB)
R/W