ADN2850BCP250 Analog Devices Inc, ADN2850BCP250 Datasheet - Page 6

• Manufacturer Part Number: ADN2850BCP250
• Description: IC DGTL RHEO DL 1024POS 16LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADN2850BCP250

• Taps: 1024
• Resistance (ohms): 250K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 3 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-LFCSP
• Resistance In Ohms: 250K
• Number Of Elements: 2
• # Of Taps: 1024
• Resistance (max): 250KOhm
• Power Supply Requirement: Single/Dual
• Interface Type: Serial (4-Wire/SPI)
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): ±2.5V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): ±2.25V
• Dual Supply Voltage (max): ±2.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADN2850-25EBZ - BOARD EVALUATION FOR ADN2850-25
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

ADN2850
Timing Diagrams
CPOL = 1
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB OF THE CHARACTER PREVIOUSLY TRANSMITTED.
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
CPOL = 0
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
SDO
CLK
RDY
CS
SDI
SDO
RDY
CLK
SDI
CS
HIGH
OR LOW
HIGH
OR LOW
t
t
14
14
t
8
t
8
t
t
B23 (MSB IN)
2
2
B23 (MSB OUT)
B24*
B23
t
B23 (MSB)
t
5
4
B23 (MSB)
t
t
1
1
t
10
B23
t
t
4
5
t
6
Figure 2. CPHA = 1 Timing Diagram
Figure 3. CPHA = 0 Timing Diagram
t
7
t
6
CPHA = 1
t
10
Rev. C | Page 6 of 28
t
7
CPHA = 0
t
11
B0 (LSB)
B0 (LSB)
t
11
B0
B0 (LSB)
B0
B0 (LSB)
t
3
t
3
*
t
t
9
15
t
t
15
9
t
12
t
t
17
12
t
17
t
16
t
16
t
13
HIGH
OR LOW
t
13
HIGH
OR LOW