AD5530BRUZ Analog Devices Inc, AD5530BRUZ Datasheet

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AD5530BRUZ

Manufacturer Part Number
AD5530BRUZ
Description
IC DAC 12BIT SRL IN/VOUT 16TSSOP
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD5530BRUZ

Data Interface
Serial
Settling Time
20µs
Number Of Bits
12
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
60mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Resolution (bits)
12bit
Sampling Rate
50kSPS
Input Channel Type
Serial
Supply Voltage Range - Analogue
± 10.8V To ± 13.2V, ± 13.5V To ± 16.5V
Supply Current
2mA
Package
16TSSOP
Resolution
12 Bit
Conversion Rate
50 KSPS
Architecture
R-2R
Digital Interface Type
Serial (3-Wire, SPI, QSPI, Microwire)
Number Of Outputs Per Chip
1
Output Type
Voltage
Full Scale Error
±2 LSB
Integral Nonlinearity Error
±1 LSB
Maximum Settling Time
20(Typ) us
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5530BRUZ
Manufacturer:
AD
Quantity:
20 000
Part Number:
AD5530BRUZ-REEL7
Manufacturer:
SAGAMI
Quantity:
12 000
a
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REFAGND
REFIN
RBEN
LDAC
SDIN
V
GND
SS
FUNCTIONAL BLOCK DIAGRAM
R
V
DD
SHIFT REGISTER
SCLK
DAC REGISTER
+
R
SYNC
12-/14-BIT DAC
SDO
GENERAL DESCRIPTION
The AD5530 and AD5531 are single 12-/14-bit serial input,
voltage output DACs, respectively.
They utilize a versatile 3-wire interface that is compatible with
SPI
Data is presented to the part in the format of a 16-bit serial word.
Serial data is available on the SDO pin for daisy-chaining pur-
poses. Data readback allows the user to read the contents of the
DAC register via the SDO pin.
The DAC output is buffered by a gain of 2 amplifier and refer-
enced to the potential at DUTGND. LDAC may be used to update
the output of the DAC asynchronously. A power-down (PD) pin
allows the DAC to be put into a low power state, and a CLR pin
allows the output to be cleared to a user-defined voltage, the
potential at DUTGND.
The AD5530 and AD5531 are available in 16-lead TSSOP
packages.
, QSPI
CONTROL LOGIC
POWER-DOWN
AD5530/AD5531
Serial Input, Voltage Output
+
, MICROWIRE
R
R
V
DUTGND
CLR
PD
AD5530/AD5531
OUT
, and DSP interface standards.
12-/14-Bit DACs

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AD5530BRUZ Summary of contents

Page 1

REFIN REFAGND LDAC RBEN SDIN SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. Serial Input, Voltage Output GENERAL DESCRIPTION The AD5530 and AD5531 are single 12-/14-bit serial input, voltage output DACs, ...

Page 2

AD5530/AD5531–SPECIFICATIONS Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error 2 Gain Temperature Coefficient 2 REFERENCE INPUTS Reference Input Range DC Input Resistance Input Current 2 DUTGND INPUT DC Input Impedance Max Input Current Input Range ...

Page 3

SPECIFICATIONS ( kΩ and C = 220 pF to GND Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error 2 Gain Temperature ...

Page 4

AD5530/AD5531 STANDALONE TIMING CHARACTERISTICS kΩ and C = 220 pF to GND. All specifications Parameter Limit at T MIN f 7 MAX t 140 ...

Page 5

DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS = –15 V ±10%; GND = –16 Parameter Limit at T MIN f 2 MAX t 500 1 t 200 2 t 200 ...

Page 6

AD5530/AD5531 ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted GND . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

Pin Mnemonic Function For bipolar ± output range, this pin should be tied REFAGND 2 REFIN This is the voltage reference input for the DAC. Connect to external +5 V reference for specified bipolar ...

Page 8

AD5530/AD5531–Typical Performance Characteristics 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 500 1000 1500 2000 2500 code 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 500 1000 1500 2000 2500 code 2 ...

Page 9

REFAGND = POSITIVE INL 1 0 NEGATIVE INL –1 –2 –3 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFIN VOLTAGE – +15V –15V SS ...

Page 10

AD5530/AD5531 V OUT PD GENERAL DESCRIPTION DAC Architecture The AD5530/AD5531 are pin-compatible 12-/14-bit DACs. The AD5530 consists of a straight 12-bit R-2R voltage mode DAC, while the AD5531 consists of a 14-bit R-2R section. Using reference connected ...

Page 11

V OUT 6 REFIN 8 AD586 AD5530 AD5531 10k DUTGND REFAGND V SS SIGNAL GND –15V ADDITIONAL PINS OMITTED FOR CLARITY ± MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5530/AD5531 is via a ...

Page 12

AD5530/AD5531 The 68HC11 is configured for master mode, MSTR= 1, CPOL = 0, and CPHA = 1. When data is transferred to the part, PC7 is taken low and data is transmitted MSB first. Data appear- ing on the MOSI ...

Page 13

OUTLINE DIMENSIONS Dimensions shown in millimeters 16-Lead Thin Shrink SO Package (TSSOP) (RU-16) 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 COPLANARITY 1.20 0.15 MAX 0.05 0.30 0.65 0.20 SEATING BSC 0.19 PLANE 0.09 ...

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