AD5530BRUZ Analog Devices Inc, AD5530BRUZ Datasheet - Page 10

• Manufacturer Part Number: AD5530BRUZ
• Description: IC DAC 12BIT SRL IN/VOUT 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5530BRUZ

• Data Interface: Serial
• Settling Time: 20µs
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 50kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: ± 10.8V To ± 13.2V, ± 13.5V To ± 16.5V
• Supply Current: 2mA
• Package: 16TSSOP
• Resolution: 12 Bit
• Conversion Rate: 50 KSPS
• Architecture: R-2R
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: ±2 LSB
• Integral Nonlinearity Error: ±1 LSB
• Maximum Settling Time: 20(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5530/AD5531
GENERAL DESCRIPTION
DAC Architecture
The AD5530/AD5531 are pin-compatible 12-/14-bit DACs.
The AD5530 consists of a straight 12-bit R-2R voltage mode DAC,
while the AD5531 consists of a 14-bit R-2R section. Using a +5 V
reference connected to the REFIN pin and REFAGND tied to
0 V, a bipolar ± 10 V voltage output results. The DAC coding is
straight binary.
Serial Interface
Serial data on the SDIN input is loaded to the input register under
the control of SCLK, SYNC, and LDAC. A write operation
transfers a 16-bit word to the AD5530/AD5531. Figures 1 and 2
show the timing diagrams. Figure 3 shows the contents of the
input shift register. Twelve or 14 bits of the serial word are data
bits; the rest are don’t cares.
The serial word is framed by the signal, SYNC. After a high to low
transition on SYNC, data is latched into the input shift register
on the falling edges of SCLK. There are two ways in which the
DAC register and output may be updated. The LDAC signal is
examined on the falling edge of SYNC; depending on its status,
either a synchronous or asynchronous update is selected. If
LDAC is low, then the DAC register and output are updated on
the low to high transition of SYNC. Alternatively, if LDAC is
high upon sampling, the DAC register is not loaded with the
new data on a rising edge of SYNC. The contents of the DAC
register and the output voltage will be updated by bringing
LDAC low any time after the 16-bit data transfer is complete.
LDAC may be tied permanently low if required. A simplified
diagram of the input loading circuitry is illustrated in Figure 4.
DB15 (MSB)
DB15 (MSB)
X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
X X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
V
PD
OUT
DATA BITS
DATA BITS
V
V
REFIN = +5V
REFAGND = 0V
T
DD
SS
A
= +25 C
= –15V
= +15V
2V/DIV
2V/DIV
DB0 (LSB)
DB0 (LSB)
Data written to the part via SDIN is available on the SDO pin
16 clocks later if the readback function is not used. SDO data is
clocked out on the falling edge of the serial clock with some delay.
PD Function
The PD pin allows the user to place the device into power-down
mode. While in this mode, power consumption is at a minimum;
the device draws only 50µA of current. The PD function does
not affect the contents of the DAC register.
READBACK Function
The AD5530/AD5531 allows the data contained in the DAC
register to be read back if required. The pins involved are the
RBEN and SDO (serial data out). When RBEN is taken low, on
the next falling edge of SCLK, the contents of the DAC register
are transferred to the shift register. RBEN may be used to frame
the readback data by leaving it low for 16 clock cycles, or it may
be asserted high after the required hold time. The shift register
contains the DAC register data and this is shifted out on the
SDO line on each falling edge of SCLK with some delay. This
ensures the data on the serial data output pin is valid for the
falling edge of the receiving part. The two MSBs of the 16-bit
word will be ‘0’s.
CLR Function
The falling edge of CLR causes V
potential as DUTGND. The contents of the registers remain
unchanged, so the user can reload the previous data with LDAC
after CLR is asserted high. Alternatively, if LDAC is tied low,
the output will be loaded with the contents of the DAC register
automatically after CLR is brought high.
Output Voltage
The DAC transfer function is as follows:
where:
D is the decimal data word loaded to the DAC register,
N is the resolution of the DAC.
Bipolar Configuration
Figure 5 shows the AD5530/AD5531 in a bipolar circuit configu-
ration. REFIN is driven by the AD586, 5 V reference, while the
REFAGND and DUTGND pins are tied to GND. This results
in a bipolar output voltage ranging from –10 V to +10 V. Resistor
R1 is provided (if required) for gain adjust. Figure 6 shows the
transfer function of the DAC when REFAGND is tied to 0 V.
V
OUT
=
2 2
[
×



REFIN
REFIN
LDAC
SYNC
SDIN
–
REFAGND
SYNC REGISTER
DAC REGISTER
16-BIT SHIFT
12-/14-BIT DAC
×
REGISTER
2
D
N



OUT
+
14
14
14
2
×
to be reset to the same
R F
E AGND
OUTPUT
SDO
−
REFIN
] –
DUTGND