AD5530BRUZ Analog Devices Inc, AD5530BRUZ Datasheet - Page 12

• Manufacturer Part Number: AD5530BRUZ
• Description: IC DAC 12BIT SRL IN/VOUT 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5530BRUZ

• Data Interface: Serial
• Settling Time: 20µs
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 50kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: ± 10.8V To ± 13.2V, ± 13.5V To ± 16.5V
• Supply Current: 2mA
• Package: 16TSSOP
• Resolution: 12 Bit
• Conversion Rate: 50 KSPS
• Architecture: R-2R
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: ±2 LSB
• Integral Nonlinearity Error: ±1 LSB
• Maximum Settling Time: 20(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5530/AD5531
The 68HC11 is configured for master mode, MSTR= 1,
CPOL = 0, and CPHA = 1. When data is transferred to the part,
PC7 is taken low and data is transmitted MSB first. Data appear-
ing on the MOSI output is valid on the falling edge of SCK. Eight
falling clock edges occur in the transmit cycle, so in order to load
the required 16-bit word, PC7 is not brought high until the second
8-bit word has been transferred to the DAC’s input shift register.
LDAC is controlled by the PC6 port output. The DAC can be
updated after each 2-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. If CLR
were used, it could be controlled by port output PC5. In order to
read data back from the DAC register, the SDO line could be
connected to MISO of the MC68HC11, with RBEN tied to another
port output controlling and framing the readback data transfer.
APPLICATIONS
Optocoupler Interface
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in excess
of 3 kV. The serial loading structure of the AD5530/AD5531
makes it ideal for opto-isolated interfaces as the number of
interface lines is kept to a minimum. Figure 10 shows a 4- channel
isolated interface to the AD5530/AD5531. To reduce the
number of opto-isolators, if simultaneous updating is not re-
quired, then the LDAC pin may be tied permanently low.
SERIAL CLOCK OUT
SERIAL DATA OUT
CONTROLLER
CONTROL OUT
SYNC
SCLK
SDIN
SYNC OUT
SCLK
SDIN
SYNC
AD5530/AD5531
V
CC
V
*ADDITIONAL PINS OMITTED FOR CLARITY
SDO
DD
TO LDAC
TO SYNC
TO SCLK
TO SDIN
R
SCLK
SDIN
SYNC
AD5530/AD5531
Serial Interface to Multiple AD5530s or AD5531s
Figure 11 shows how the SYNC pin is used to address multiple
AD5530/AD5531s. All devices receive the same serial clock and
serial data, but only one device will receive the SYNC signal at any
one time. The DAC addressed will be determined by the decoder.
There will be some feedthrough from the digital input lines, the
effects of which can be minimized by using a burst clock.
Daisy-Chaining Interface with Multiple AD5530s or AD5531s
A number of these DAC parts may be daisy-chained together
using the SDO pin. Figure 12 illustrates such a configuration.
SDO
ADDRESS
ENABLE
CODED
OMITTED FOR CLARITY
ADDITIONAL PINS
R
EN
SCLK
SDIN
SYNC
DECODER
AD5530/AD5531
SCLK
SDIN
DGND
V
CC
SDO
TO OTHER
SERIAL DEVICES
R
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
AD5530/AD5531
AD5530/AD5531
AD5530/AD5531
AD5530/AD5531
V
V
V
V
OUT
OUT
OUT
OUT