AD5530BRUZ Analog Devices Inc, AD5530BRUZ Datasheet - Page 7

• Manufacturer Part Number: AD5530BRUZ
• Description: IC DAC 12BIT SRL IN/VOUT 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5530BRUZ

• Data Interface: Serial
• Settling Time: 20µs
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 50kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: ± 10.8V To ± 13.2V, ± 13.5V To ± 16.5V
• Supply Current: 2mA
• Package: 16TSSOP
• Resolution: 12 Bit
• Conversion Rate: 50 KSPS
• Architecture: R-2R
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: ±2 LSB
• Integral Nonlinearity Error: ±1 LSB
• Maximum Settling Time: 20(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the maximum
deviation, in LSBs, from a straight line passing through the end-
points of the DAC transfer function.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is a measure of the output error when all 0s are
loaded to the DAC latch.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 V
Mnemonic
REFAGND
REFIN
LDAC
SDIN
SYNC
RBEN
SCLK
SDO
CLR
PD
GND
NC
V
DUTGND
V
V
SS
OUT
DD
Function
For bipolar ± 10 V output range, this pin should be tied to 0 V.
This is the voltage reference input for the DAC. Connect to external +5 V reference for specified bipolar
± 10 V output.
Load DAC logic input (active low). When taken low, the contents of the shift register are transferred to
the DAC register. LDAC may be tied permanently low enabling the outputs to be updated on the rising
edge of SYNC.
Serial data input. This device accepts 16-bit words. Data is clocked into the input register on the falling
edge of SCLK.
Active low control input. Data is clocked into the shift requester on the falling edges of SCLK.
Active low readback enable function. This function allows the contents of the DAC register to be read.
Data from the DAC register will be shifted out on SDO pin on each rising edge of SCLK.
Clock input. Data is clocked into the input register on the falling edge of SCLK.
Serial data out. This pin is used to clock out the serial data previously written to the input shift register or
may be used in conjunction with RBEN to read back the data from the DAC register. This is an open
drain output; it should be pulled high with an external pull-up resistor. In standalone mode, SDO should
be tied to GND or left high impedance.
Level sensitive, active low input. A falling edge of CLR resets V
registers are untouched.
This allows the DAC to be put into a power-down state.
Ground reference
Do not connect anything to this pin.
Negative analog supply voltage, –12 V ± 10% or –15 V ± 10% for specified performance.
V
DAC output
Positive analog supply voltage, +12 V ± 10% or +15 V ± 10% for specified performance.
OUT
is referenced to the voltage applied to this pin.
REF
– 1 LSB.
PIN FUNCTION DESCRIPTIONS
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is the
deviation in slope of the DAC transfer characteristic from ideal.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-s and is mea-
sured when the digital input code is changed by 1 LSB at the
major carry transition.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. It is specified
in nV-s and is measured with a full-scale code change on the data
bus, i.e., from all 0s to all 1s and vice versa.
OUT
to DUTGND. The contents of the
AD5530/AD5531