AD9767ASTZ Analog Devices Inc, AD9767ASTZ Datasheet - Page 20
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AD9767ASTZ
Manufacturer Part Number
AD9767ASTZ
Description
IC DAC 14BIT DUAL 125MSPS 48LQFP
Manufacturer
Analog Devices Inc
Series
TxDAC+®r
Specifications of AD9767ASTZ
Data Interface
Parallel
Settling Time
35ns
Number Of Bits
14
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
450mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
14bit
Sampling Rate
125MSPS
Input Channel Type
Parallel
Supply Voltage Range - Analog
3V To 5.5V
Supply Voltage Range - Digital
2.7V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9767-EBZ - BOARD EVAL FOR AD9767
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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AD9763/AD9765/AD9767
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of
the actual analog output from the ideal output, determined by
a straight line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized to
full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the ideal of
zero. For I
For I
Gain Error
Gain error is the difference between the actual and ideal output
spans. The actual span is determined by the output when all inputs
are set to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits may cause either output stage
saturation or breakdown resulting in nonlinear performance.
OUTB
, 0 mA output is expected when all inputs are set to 1s.
OUTA
, 0 mA output is expected when the inputs are all 0s.
Rev. F | Page 20 of 44
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T
offset and gain drift, the drift is reported in part per million (ppm)
of full-scale range (FSR) per degree Celsius. For reference drift,
the drift is reported in ppm per degree Celsius (ppm/°C).
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from nominal to minimum and maximum
specified voltages.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band about its final value,
measured from the start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in picovolts per second (pV-s).
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal.
It is expressed as a percentage or in decibels (dB).
MIN
or T
MAX
. For