AD9767ASTZ Analog Devices Inc, AD9767ASTZ Datasheet - Page 33
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AD9767ASTZ
Manufacturer Part Number
AD9767ASTZ
Description
IC DAC 14BIT DUAL 125MSPS 48LQFP
Manufacturer
Analog Devices Inc
Series
TxDAC+®r
Specifications of AD9767ASTZ
Data Interface
Parallel
Settling Time
35ns
Number Of Bits
14
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
450mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
14bit
Sampling Rate
125MSPS
Input Channel Type
Parallel
Supply Voltage Range - Analog
3V To 5.5V
Supply Voltage Range - Digital
2.7V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9767-EBZ - BOARD EVAL FOR AD9767
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9767ASTZ
Manufacturer:
ADI
Quantity:
3 000
Company:
Part Number:
AD9767ASTZ
Manufacturer:
ADI
Quantity:
181
Company:
Part Number:
AD9767ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9767ASTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9767ASTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
I and Q digital data can be fed into the AD9763 in two ways. In
dual-port mode, the digital I information drives one input port,
and the digital Q information drives the other input port. If no
interpolation filter precedes the DAC, the symbol rate is the rate
at which the system clock drives the CLK and WRT pins on the
AD9763. In interleaved mode, the digital input stream at Port 1
contains the I and the Q information in alternating digital words.
Using IQSEL and IQRESET, the AD9763 can be synchronized to
the I and Q data streams. The internal timing of the AD9763 routes
the selected I and Q data to the correct DAC output. In interleaved
mode, if no interpolation filter precedes the AD9763, the symbol
rate is half that of the system clock driving the digital data stream
and the IQWRT and IQCLK pins on the AD9763.
CDMA
Code division multiple access (CDMA) is an air transmit/receive
scheme in which the signal in the transmit path is modulated
with a pseudorandom digital code (sometimes referred to as the
spreading code). The effect of this is to spread the transmitted
signal across a wide spectrum. Similar to a discrete multitone
(DMT) waveform, a CDMA waveform containing multiple
subscribers can be characterized as having a high peak to average
ratio (that is, crest factor), thus demanding highly linear
components in the transmit signal path. The bandwidth of the
spectrum is defined by the CDMA standard being used, and in
operation it is implemented by using a spreading code with
particular characteristics.
Distortion in the transmit path can lead to power being transmitted
out of the defined band. The ratio of power transmitted in-band to
Rev. F | Page 33 of 44
out-of-band is often referred to as adjacent channel power (ACP).
This is a regulatory issue due to the possibility of interference with
other signals being transmitted by air. Regulatory bodies define a
spectral mask outside of the transmit band, and the ACP must fall
under this mask. If distortion in the transmit path causes the
ACP to be above the spectral mask, filtering or different
component selection is needed to meet the mask requirements.
Figure 85 shows the results of using the AD9763/AD9765/
AD9767 with the AD8346 to reconstruct a wideband CDMA
signal centered at 2.4 GHz. The baseband signal is sampled at
65 MSPS and has a chip rate of 8 MHz.
Figure 85. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS, Recreated at
–100
–110
–120
–130
–
–40
–50
–60
–70
–80
–90
30
CENTER 2.4GHz
==
c11
2.4 GHz, Adjacent Channel Power >60 dBm
c11
C0
AD9763/AD9765/AD9767
FREQUENCY
3MHz
cu1
C0
SPAN 30MHz
cu1