MAX5550ETE+ Maxim Integrated Products, MAX5550ETE+ Datasheet - Page 11

• Manufacturer Part Number: MAX5550ETE+
• Description: IC DAC 10BIT DUAL 30MA 16-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5550ETE+

• Settling Time: 30µs
• Number Of Bits: 10
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Conversion Rate: 10 MSPs
• Resolution: 10 bit
• Interface Type: Serial (SPI, I2C)
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 6 mA
• Voltage Reference: Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A master initiates communication with a slave device
by issuing a START condition followed by a slave
address (see Table 3). The slave address consists of 7
address bits and a read/write bit (R/W). When idle, the
device continuously waits for a START condition fol-
lowed by its slave address. When the device recog-
nizes its slave address, it acquires the data and
executes the command. The first 5 bits (MSBs) of the
slave address have been factory programmed and are
always 01100. Connect A1 and A0 to V
program the remaining 2 bits of the slave address. Set
the least significant bit (LSB) of the address byte (R/W)
to zero to write to the MAX5550. After receiving the
address, the MAX5550 (slave) issues an acknowledge
by pulling SDA low for one clock cycle. I
mands (R/W = 1) are not acknowledged by the
MAX5550.
The write command requires 27 clock cycles. In write
mode (R/W = 0), the command/data byte that follows
the address byte controls the MAX5550 (Table 3). The
registers update on the rising edge of the 26th SCL
*Read operation not supported.
Figure 5. Acknowledge Condition
Table 3. Write Operation
Master
Slave
SDA
SDA
S
T
A
R
T
S
0
1
______________________________________________________________________________________
ADDRESS
1
BYTE
SDA
SCL
0
0 A1 A0 0
S
Dual, 10-Bit, Programmable, 30mA
R/ W*
A
C
K
Slave Address
1
DD
2
C5
C read com-
Write Cycle
or GND to
C4 C3
COMMAND/DATA BYTE
2
High-Output-Current DAC
C2 C1
pulse. Prematurely aborting the write cycle does not
update the DAC. See Table 4 for a command summary.
The MAX5550 is compatible with the 3-wire SPI serial
interface (Figure 6). This interface mode requires three
inputs: chip-select (CS), data clock (SCLK), and data in
(DIN). Drive CS low to enable the serial interface and
clock data synchronously into the shift register on each
SCLK rising edge.
The MAX5550 requires 16 clock cycles to clock in 6
command bits (C5–C0) and 10 data bits (D9–D0)
(Figure 7). After loading data into the shift register,
drive CS high to latch the data into the appropriate
DAC register and disable the serial interface. Keep CS
low during the entire serial data stream to avoid corrup-
tion of the data. See Table 4 for a command summary.
The MAX5550 has a software shutdown mode that
reduces the supply current to less than 1µA. Shutdown
mode disables the DAC outputs. The serial interface
remains active in shutdown. This provides the flexibilty to
update the registers while in shut down. Recycling the
power supply resets the device to the default settings.
C0 D9
ACKNOWLEDGE
8
SPI Compatibility (SPI/ I2C = V
D8
A
C
K
9
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
Shutdown Mode
A
C
K
DD
11
S
T
O
P
P
)