MAX5550ETE+ Maxim Integrated Products, MAX5550ETE+ Datasheet - Page 4

• Manufacturer Part Number: MAX5550ETE+
• Description: IC DAC 10BIT DUAL 30MA 16-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5550ETE+

• Settling Time: 30µs
• Number Of Bits: 10
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Conversion Rate: 10 MSPs
• Resolution: 10 bit
• Interface Type: Serial (SPI, I2C)
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 6 mA
• Voltage Reference: Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
ELECTRICAL CHARACTERISTICS (continued)
(V
V
Note 1: 100% production tested at T
Note 2: INL linearity is guaranteed from code 60 to code 1024.
Note 3: Connect a resistor from FSADJ_ to GND to adjust the full-scale current. See the Reference Architecture and Operation section.
Note 4: Settling time is measured from (0.25 x full scale) to (0.75 x full scale).
Note 5: The device draws higher supply current when the digital inputs are driven with voltages between (V
4
Bus Free Time Between a STOP
and START Condition
Setup Time for STOP Condition
Maximum Capacitive Load for
Each Bus Line
SPI TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
DIN Setup Time
DIN Hold Time
SCLK Fall to DOUT Transition
CS Fall to DOUT Enable
CS Rise to DOUT Disable
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse-Width High
SPI TIMING CHARACTERISTICS FOR DAISY CHAINING (Figure 6)
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
DIN Setup Time
DIN Hold Time
SCLK Fall to DOUT Transition
CS Fall to DOUT Enable
CS Rise to DOUT Disable
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse-Width High
SCLK/SCL
DD
_______________________________________________________________________________________
= +2.7V to +5.25V, GND = 0, V
0.5V). See the Supply Current vs. Digital Input Voltage graph in the Typical Operating Characteristics.
PARAMETER
= 0, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
A
SYMBOL
t
= +25°C. Limits over temperature are guaranteed by design.
SU:STO
t
t
REFIN
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CSW
CSW
t
CSH
t
DO1
CSD
t
CSH
t
DO1
CSD
BUF
C
t
t
CSS
t
CSE
CS0
CS1
t
t
CSS
t
CSE
CS0
CS1
CH
DH
CH
DH
CP
CL
DS
CP
CL
DS
B
= +1.25V, internal reference, R
C
C
C
C
C
C
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
CONDITIONS
FSADJ_
DD
= 20kΩ; compliance voltage = (V
= +3.0V and T
MIN
160
100
100
200
100
1.3
40
40
25
50
40
50
40
80
80
25
50
40
50
40
0
0
A
= +25°C.) (Note 1)
TYP
400
DD
- 0.5V) and (GND +
MAX
40
40
40
40
40
40
DD
UNITS
- 0.6V),
pF
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns