AD5763CSUZ Analog Devices Inc, AD5763CSUZ Datasheet - Page 20

• Manufacturer Part Number: AD5763CSUZ
• Description: DAC 16BIT DUAL 5V 2LSB 32-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5763CSUZ

• Data Interface: Serial
• Design Resources: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5763 (CN0074)
• Settling Time: 8µs
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 45mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Resolution (bits): 16bit
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5763
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9). The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel
by −32 LSB to +31 LSB in 1 LSB increments as shown in Table 15 and Table 16. The adjustment is made to both the positive full-scale and
negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos complement.
Table 15. Programming Fine Gain Register
REG2
1
Table 16. Fine Gain Register Options
Gain Adjustment
+31 LSB
+30 LSB
…
No Adjustment (Default)
…
−31 LSB
−32 LSB
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC channel the data transfer is to
take place (see Table 9). The AD5763 offset register is an 8-bit register and allows the user to adjust the offset of each channel by −16 LSB
to +15.875 LSB in increments of ⅛ LSB as shown in Table 17 and Table 18. The offset register coding is twos complement.
Table 17. Programming the Offset Register
REG2
1
Table 18. Offset Register Options
Offset Adjustment
+15.875 LSB
+15.75 LSB
…
No Adjustment (Default)
…
−15.875 LSB
−16 LSB
REG1
0
REG1
0
REG0
1
REG0
0
A2
DAC address
A2
A1
FG5
0
0
…
0
…
1
1
DAC address
A1
A0
OF7
0
0
…
0
…
1
1
A0
DB15:DB8
Don’t care
FG4
1
1
…
0
…
0
0
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OF6
1
1
…
0
…
0
0
DB15:DB6
Don’t care
DB7
OF7
OF5
1
1
…
0
…
0
0
FG3
1
1
…
0
…
0
0
DB6
OF6
OF4
1
1
…
0
…
0
0
DB5
FG5
DB5
OF5
FG2
1
1
…
…
0
0
0
OF3
1
1
…
0
…
0
0
DB4
FG4
DB4
OF4
DB3
FG3
OF2
1
1
…
0
…
0
0
DB3
OF3
FG1
1
1
…
0
…
0
0
DB2
FG2
DB2
OF2
OF1
1
1
…
0
…
0
0
DB1
FG1
DB1
OF1
FG0
1
0
…
0
…
1
0
OF0
1
0
…
…
1
0
0
DB0
FG0
DB0
OF0