CS4360-DZZR Cirrus Logic Inc, CS4360-DZZR Datasheet - Page 26

• Manufacturer Part Number: CS4360-DZZR
• Description: IC DAC STER 6CH 102DB 28-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4360-DZZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 6
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 265mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

4.9.1
The MAP byte precedes the control port register byte during a write operation and is not available again
until after a start condition is initiated. During a read operation the byte transmitted after the ACK will con-
tain the data of the register pointed to by the MAP (see sections 4.9.1a and 4.9.3 for write/read details).
4.9.1a
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto increment after each byte is written, allowing block reads or writes of successive registers.
4.9.1b
4.9.2
In the I²C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip address
(001000[AD0][R/W]) and should be tied to VLC or GND as required, before powering up the device. If the
device ever detects a high-to-low transition on the AD0/CS pin after power-up, SPI mode will be selected.
4.9.2a
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions in section 3.
1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
2) Wait for an acknowledge (ACK) from the device, then write to the memory address pointer, MAP. This
3) Wait for an acknowledge (ACK) from the device, then write the desired data to the register pointed to
4) If the INCR bit (see section 4.9.1a) is set to 1, repeat the previous step until all the desired registers
5) If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to repeat
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001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
byte points to the register to be written.
by the MAP.
are written, then initiate a STOP condition to the bus.
the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP
condition to the bus.
INCR
7
0
Memory Address Pointer (MAP)
I²C Mode
INCR (Auto Map Increment)
MAP0-3 (Memory Address Pointer)
I²C Write
Default = ‘0’
0 - Disabled
1 - Enabled
Default = ‘0000’
Reserved
6
0
Reserved
5
0
Reserved
4
0
MAP3
3
0
MAP2
2
0
MAP1
1
0
CS4360
MAP0
DS517F2
0
0