CS4360-DZZR Cirrus Logic Inc, CS4360-DZZR Datasheet - Page 35

• Manufacturer Part Number: CS4360-DZZR
• Description: IC DAC STER 6CH 102DB 28-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4360-DZZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 6
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 265mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

6.6
DS517F2
Reserved
6.5.5
6.5.6
6.5.7
6.6.1
7
0
REVISION REGISTER (READ ONLY) (ADDRESS 0DH)
Function:
Function:
Function:
Function:
FREEZE CONTROLS (FREEZE)
MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
SINGLE VOLUME CONTROL (SNGLVOL)
REVISION INDICATOR (REV) [READ ONLY]
Default = 0
0 - Disabled
1 - Enabled
This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To have multiple changes in the control port registers take effect simulta-
neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
Default = 0
0 - Disabled
1 - Enabled
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.
Default = 0
0 - Disabled
1 - Enabled
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. When enabled, the volume on all channels is determined by the
A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored.
Default = none
0001 - Revision A
0010 - Revision B
0011 - Revision C
etc.
This read-only register indicates the revision level of the device.
Reserved
6
0
Reserved
5
0
Reserved
BIT 2
4
0
BIT 0
BIT 0-3
REV3
BIT 1
X
3
REV2
X
2
REV1
X
1
CS4360
REV0
X
0
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