CS4360-DZZR Cirrus Logic Inc, CS4360-DZZR Datasheet - Page 30

• Manufacturer Part Number: CS4360-DZZR
• Description: IC DAC STER 6CH 102DB 28-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4360-DZZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 6
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 265mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

6.
Note: All registers are read/write in I²C mode and write only in SPI, unless otherwise stated.
6.1
30
AMUTE
6.1.1
6.1.2
REGISTER DESCRIPTIONS
7
1
MODE CONTROL 1 (ADDRESS 01H)
Function:
Function:
AUTO-MUTE (AMUTE)
DIGITAL INTERFACE FORMAT (DIF)
DIF2
Default = 1
0 - Disabled
1 - Enabled
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or 1. A single sample of non-static data will release the mute. Detection and muting
is done independently for each channel. The quiescent voltage on the output will be retained and the
Mute Control pin will become active during the mute period. The muting function is affected, similar
to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 15-17.
0
0
0
0
1
1
1
1
DIF2
6
0
DIF1
0
0
1
1
0
0
1
1
Table 8. Digital Interface Formats - Control Port Mode
DIF1
DIF0
5
0
0
1
0
1
0
1
0
1
BIT 7
Left Justified, up to 24-bit data
I
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
2
S, up to 24-bit data
DIF0
4
0
BIT 4-6
DESCRIPTION
DEM1
3
0
DEM0
2
0
Format
0
1
2
3
4
5
-
-
FM1
1
0
FIGURE
15
16
17
17
17
17
-
-
CS4360
DS517F2
FM0
0
0