K4S561632J-UC60000 Samsung Semiconductor, K4S561632J-UC60000 Datasheet - Page 4
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K4S561632J-UC60000
Manufacturer Part Number
K4S561632J-UC60000
Description
Manufacturer
Samsung Semiconductor
Type
SDRAMr
Datasheet
1.K4S561632J-UC60000.pdf
(15 pages)
Specifications of K4S561632J-UC60000
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
120mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
K4S560432J
K4S560832J
K4S561632J
1.0 Features
2.0 General Description
3.0 Ordering Information
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
•
• RoHS compliant
16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Note 1 : 256Mb J-die SDR DRAMs support Lead-Free & Halogen-Free package with Lead-Free package code(-U).
Lead-Free & Halogen-Free Package
The K4S560432J / K4S560832J / K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
K4S560432J-U
K4S560832J-UC/L75
K4S561632J-UC/L50
K4S561632J-UC/L60
K4S561632J-UC/L75
Part No.
*1
C/L75
Organization
Orgainization
16Mx16
16M x 16
64Mx4
32Mx8
64M x 4
32M x 8
Row & Column address configuration
133MHz (CL=3)
133MHz (CL=3)
200MHz (CL=3)
166MHz (CL=3)
133MHz (CL=3)
Row Address
Max Freq.
A0~A12
A0~A12
A0~A12
4 of 15
Interface
Column Address
LVTTL
A0-A9, A11
A0-A9
A0-A8
Synchronous DRAM
Lead-Free & Halogen-Free
Rev. 1.22 August 2008
54pin TSOP(II)
Package
*1