MT4JTF12864AZ-1G4D1 Micron Technology Inc, MT4JTF12864AZ-1G4D1 Datasheet - Page 4

• Manufacturer Part Number: MT4JTF12864AZ-1G4D1
• Description: MOD DDR3 SDRAM 1GB 240UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT4JTF12864AZ-1G4D1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 240UDIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 1.34A
• Number Of Elements: 4
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Memory Type: DDR3 SDRAM
• Memory Size: 1GB
• Speed: 1333MT/s
• Features: -
• Package / Case: 240-UDIMM
• Lead Free Status / Rohs Status: Compliant

Table 6: Pin Descriptions
PDF: 09005aef83cad6ed
JTF4C64_128x64AZ.pdf – Rev. A 10/09
RAS#, CAS#,
DQS#[7:0]
DQS[7:0],
DQ[63:0]
Symbol
CK#[1:0]
CK[1:0],
DM[7:0]
BA[2:0]
A[13:0]
RESET#
SA[2:0]
V
V
V
ODT0
CKE0
WE#
SDA
V
DDSPD
S0#
SCL
REFDQ
REFCA
V
DD
SS
Supply
Supply
Supply
Supply
Supply
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to determine
whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also used
for BC4/BL8 identification as “BL on-the-fly” during CAS commands. The address inputs also
provide the op-code during the mode register command set. A[12:0] address the 1Gb DDR3
devices. A[13:0] address the 2Gb DDR3 devices.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2,
and MR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input sig-
nals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry
and clocks on the DRAM.
Data input mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH, along with the input data, during a write access. DM is sampled on both
edges of the DQS. Although the DM pins are input-only, the DM loading is designed to match
that of the DQ and DQS pins.
On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
Reset: An active LOW CMOS input referenced to V
put defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
Presence-detect address inputs: These pins are used to configure the temperature sensor/
SPD EEPROM address range on the I
Serial clock for presence-detect: SCL is used to synchronize the communication to and from
the temperature sensor/SPD EEPROM.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the
temperature sensor/SPD EEPROM on the module on the I
Power supply: 1.5V ±0.075V.
Serial EEPROM positive power supply: +3.0V to +3.6V. The component V
connected to the module Vdd.
Reference voltage: Control, command, and address (V
Reference voltage: DQ, DM (V
Ground.
512MB, 1GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
DD
4
/2).
2
C bus.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
SS
. The RESET# input receiver is a CMOS in-
DD
2
DD
C bus.
/2).
and DC LOW ≤ 0.2 × V
©2009 Micron Technology, Inc. All rights reserved.
DD
and V
DD
.
DDQ
are