MT4JTF12864AZ-1G4D1 Micron Technology Inc, MT4JTF12864AZ-1G4D1 Datasheet - Page 8

• Manufacturer Part Number: MT4JTF12864AZ-1G4D1
• Description: MOD DDR3 SDRAM 1GB 240UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT4JTF12864AZ-1G4D1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 240UDIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 1.34A
• Number Of Elements: 4
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Memory Type: DDR3 SDRAM
• Memory Size: 1GB
• Speed: 1333MT/s
• Features: -
• Package / Case: 240-UDIMM
• Lead Free Status / Rohs Status: Compliant

General Description
Fly-By Topology
Serial Presence-Detect EEPROM Operation
PDF: 09005aef83cad6ed
JTF4C64_128x64AZ.pdf – Rev. A 10/09
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-
ules use DDR architecture to achieve high-speed operation. DDR3 architecture is
essentially an 8n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM
module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write-leveling feature of DDR3.
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JE-
DEC standard JC-45, “Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM
Modules.” These bytes identify module-specific timing parameters, configuration infor-
mation, and physical attributes. User-specific information can be written into the
remaining 128 bytes of storage. READ/WRITE operations between the system (master)
and the EEPROM (slave) device occur via an I
Vss, permanently disabling hardware write protect. For further information please refer
to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect."
512MB, 1GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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C bus. Write protect (WP) is connected to
General Description
©2009 Micron Technology, Inc. All rights reserved.