SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 116

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

5.6
The SWC wakes up the system by sending a power-up
request to the ACPI controller in response to the following
maskable system events:
• Modem ring (RI2#)
• Audio Codec event (SDATA_IN2)
• Programmable Consumer Electronics IR (CEIR)
Each system event that is monitored by the SWC is fed into
a dedicated detector that decides when the event is active,
according to predetermined (either fixed or programmable)
criteria. A set of dedicated registers is used to determine
the wakeup criteria, including the CEIR address.
A Wakeup Events Status Register (WKSR) and a Wakeup
Events Control Register (WKCR) hold a Status bit and
Enable bit, respectively, for each possible wakeup event.
Upon detection of an active event, the corresponding Sta-
tus bit is set to 1. If the event is enabled (the corresponding
Enable bit is set to 1), a power-up request is issued to the
ACPI controller. In addition, detection of an active wakeup
event may be also routed to an arbitrary IRQ.
Disabling an event prevents it from issuing power-up
requests, but does not affect the Status bits. A power-up
reset is issued to the ACPI controller when both the Status
and Enable bits are set to 1 for at least one event type.
SWC logic is powered by V
figuration registers are battery backed, powered by V
The setup of the wakeup events, including programmable
sequences, is retained throughout power failures (no V
as long as the battery is connected. V
if V
Hardware reset does not affect the SWC registers. They
are reset only by a SIO software reset or power-up of V
5.6.1
5.6.1.1
A low-to-high transition on SDATA_IN2 indicates the
detection of an Audio Codec event and can be used as a
wakeup event.
116
Range
address
SB
Time
0
1
2
3
> 2.0; otherwise, V
System Wakeup Control (SWC)
Event Detection
Audio Codec Event
Low Limit
10h
07h
-
-
32579B
BAT
RC-5
SB
is used as the V
. The SWC control and con-
Table 5-26. Time Range Limits for CEIR Protocols
High Limit
0Bh
14h
PP
-
-
is taken from V
PP
source.
Low Limit
PP
SB
09h
14h
50h
28h
PP
SB
.
.
)
5.6.1.2
A CEIR transmission received on IRRX1 in a pre-selected
standard (NEC, RCA or RC-5) is matched against a pro-
grammable CEIR address. Detection of matching can be
used as a wakeup event. The CEIR address detection
operates independently of the serial port with the IR (which
is powered down with the rest of the system).
Whenever an IR signal is detected, the receiver immedi-
ately enters the Active state. When this happens, the
receiver keeps sampling the IR input signal and generates
a bit string where a logic 1 indicates an idle condition and a
logic 0 indicates the presence of IR energy. The received
bit string is de-serialized and assembled into 8-bit charac-
ters.
The expected CEIR protocol of the received signal should
be configured through bits [5:4] of the CEIR Wakeup Con-
trol register (IRWCR) (see Table 5-30 on page 119).
The CEIR Wakeup Address register (IRWAD) holds the
unique address to be compared with the address contained
in the incoming CEIR message. If CEIR is enabled
(IRWCR[0] = 1) and an address match occurs, then the
CEIR Event Status bit of WKSR is set to 1.
The CEIR Address Shift register (ADSR) holds the
received address which is compared with the address con-
tained in the IRWAD. The comparison is affected also by
the CEIR Wakeup Address Mask register (IRWAM) in
which each bit determines whether to ignore the corre-
sponding bit in the IRWAD.
If CEIR routing to interrupt request is enabled, the
assigned SWC interrupt request can be used to indicate
that a complete address has been received. To get this
interrupt when the address is completely received, IRWAM
should be written with FFh. Once the interrupt is received,
the value of the address can be read from ADSR.
Another parameter that is used to determine whether a
CEIR signal is to be considered valid is the bit cell time
width. There are four time ranges for the different protocols
and carrier frequencies. Four pairs of registers (IRWTRxL
and IRWTRxH) define the low and high limits of each time
range. Table 5-26 lists the recommended time ranges limits
for the different protocols and their applicable ranges. The
values are represented in hexadecimal code where the
units are of 0.1 ms.
NEC
High Limit
AMD Geode™ SC1200/SC1201 Processor Data Book
CEIR Address
0Dh
19h
64h
32h
Low Limit
0Ch
16h
B4h
23h
RCA
SuperI/O Module
High Limit
DCh
1Ch
2Dh
12h