SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 129

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

SuperI/O Module
5.8
This section briefly describes the following blocks that pro-
vide legacy device functions:
• Parallel Port. (Similar to Parallel Port in the National
• Serial Port 1 and Serial Port 2 (SP1 and SP2), UART
• Infrared Communications Port / Serial Port 3 function-
The description of each Legacy block includes a general
description, register maps, and bit maps.
AMD Geode™ SC1200/SC1201 Processor Data Book
Semiconductor PC87338.)
functionality for both SP1 and SP2. (Similar to SCC1 in
the National Semiconductor PC87338.)
ality. (Similar to SCC2 in the National Semiconductor
PC87338.)
Second Level Offset
First Level Offset
Legacy Functional Blocks
000h
000h
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
400h
401h
402h
403h
404h
405h
00h
02h
04h
05h
Table 5-34. Parallel Port Register Map for Second Level Offset
Table 5-33. Parallel Port Register Map for First Level Offset
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
W
W
Name
DATAR. PP Data
AFIFO. ECP Address FIFO
DSR. Status
DCR. Control
ADDR. EPP Address
DATA0. EPP Data Port 0
DATA1. EPP Data Port 1
DATA2. EPP Data Port 2
DATA3. EPP Data Port 3
CFIFO. PP Data FIFO
DFIFO. ECP Data FIFO
TFIFO. Test FIFO
CNFGA. Configuration A
CNFGB. Configuration B
ECR. Extended Control
EIR. Extended Index
EDR. Extended Data
EAR. Extended Auxiliary Status
Name
Control0. Control Register 0
Control2. Control Register 2
Control4. Control Register 4
PP Confg0. Parallel Port Configuration Register 0
5.8.1
The Parallel Port supports all IEEE1284 standard commu-
nication modes: Compatibility (known also as Standard or
SPP), Bidirectional (known also as PS/2), FIFO, EPP
(known also as Mode 4) and ECP (with an optional
Extended ECP mode).
5.8.1.1
The Parallel Port register maps (Table 5-33 and Table 5-34)
are grouped according to first and second level offsets.
EPP and second level offset registers are available only
when the base address is 8-byte aligned.
Parallel Port functional block bit maps are shown in Table 5-
35 and Table 5-36.
Parallel Port
Parallel Port Register and Bit Maps
32579B
Modes (ECR Bits) 7 6 5
000 or 001
All Modes
All Modes
All Modes
All Modes
All Modes
All Modes
011
100
100
100
100
100
010
011
110
111
111
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