RG82865GV S L77X Intel, RG82865GV S L77X Datasheet - Page 61
RG82865GV S L77X
Manufacturer Part Number
RG82865GV S L77X
Description
Manufacturer
Intel
Datasheet
1.RG82865GV_S_L77X.pdf
(250 pages)
Specifications of RG82865GV S L77X
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3.5.8
3.5.9
Intel
®
82865G/82865GV GMCH Datasheet
MLT—Master Latency Timer Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
Device 0 in the GMCH is not a PCI master. Therefore, this register is not implemented.
HDR—Header Type Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
7:0
7:0
Bit
Bit
Reserved.
PCI Header (HDR)—RO. This field always returns 0 to indicate that the GMCH is a single function
device with standard header layout.
0Dh
00h
RO
8 bits
0Eh
00h
RO
8 bits
Descriptions
Descriptions
Register Description
61
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