RG82865GV S L77X Intel, RG82865GV S L77X Datasheet - Page 73

• Manufacturer Part Number: RG82865GV S L77X
• Manufacturer: Intel

Specifications of RG82865GV S L77X

• Lead Free Status / Rohs Status: Not Compliant

3.5.21
Intel
®
82865G/82865GV GMCH Datasheet
ESMRAMC—Extended System Management RAM Control
(Device 0)
Address Offset:
Default Value:
Access:
Size:
The Extended SMRAM register controls the configuration of Extended SMRAM space. The
Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory
space that is above 1 MB.
2:1
Bit
7
6
5
4
3
0
Enable High SMRAM (H_SMRAME)—R/W/L. This bit controls the SMM memory space location
(i.e., above 1 MB or below 1 MB). When G_SMRAME is 1 and H_SMRAME (this bit) is set to 1, the
high SMRAM memory space is enabled. SMRAM accesses within the range 0FEDA0000h to
0FEDBFFFFh are remapped to SDRAM addresses within the range 000A0000h to 000BFFFFh.
Once D_LCK has been set, this bit becomes read only.
Invalid SMRAM Access (E_SMERR)—R/WC. This bit is set when the processor has accessed
the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM
space and with the D-OPEN bit = 0. It is software’s responsibility to clear this bit.
NOTE: Software must write a 1 to this bit to clear it.
SMRAM Cacheable (SM_CACHE)—RO. Hardwired to 1.
L1 Cache Enable for SMRAM (SM_L1)—RO. Hardwired to 1.
L2 Cache Enable for SMRAM (SM_L2)—RO. Hardwired to 1.
TSEG Size (TSEG_SZ)—R/W. This field selects the size of the TSEG memory block, if enabled.
Memory from the top of SDRAM space (TOUD +TSEG_SZ) to TOUD is partitioned away so that it
may only be accessed by the processor interface and only then when the SMM bit is set in the
request packet. Non-SMM accesses to this memory region are sent to HI when the TSEG memory
block is enabled.
00 =Reserved
01 =Reserved
10=(TOUD + 512 KB) to TOUD
11 =(TOUD + 1 MB) to TOUD
TSEG Enable (T_EN)—R/W/L. This bit enables SMRAM memory for Extended SMRAM space
only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate
physical address space. Note that once D_LCK is set, this bit becomes read only.
9Eh
38h
R/W, R/WC, RO, Lock
8 bits
Descriptions
Register Description
73