RG82865GV S L77X Intel, RG82865GV S L77X Datasheet - Page 68

• Manufacturer Part Number: RG82865GV S L77X
• Manufacturer: Intel

Specifications of RG82865GV S L77X

• Lead Free Status / Rohs Status: Not Compliant

Register Description
3.5.17
68
FPLLCONT— Front Side Bus PLL Clock Control Register
(Device 0)
Address Offset:
Default Value:
Access:
Size:
These register bits are used for changing DDR frequency initializing GMCH memory and I/O
clocks WIO DLL delays, and initializing internal graphics controller's clocks and resets.
Bit
7:5
4
3
2
1
0
Reserved.
Memory and Memory I/O DLL Clock Gate (DLLCKGATE)—R/W.
0 = Writing a 0 will cleanly re-enable the memory and memory I/O clocks from the DLL outputs.
1 = Writing a 1 will cleanly disable the memory and memory IO clocks of the chipset core and
NOTE: This bit should always be written to before writing to the FPLLSYNC bit.
Graphics Activate (GFXACT)—R/W.
1 = After propagating the internal graphics enable, writing a 1 to this bit will cause the internal
Propagate Internal Graphics Enable (PIGE)—R/W.
0 = This bit should be set to 0 shortly after setting it to 1, though no action is taken on writing a 0.
1 = After writing a 0 to IGDIS (Dev 0, Offset 52, bit 3) to enable internal graphics, writing a 1 to
FSB PLL Sync (FPLLSYNC)—R/W.
0 = After writing a 1, writing a 0 will cause the FSB PLL to synchronize the memory and graphics
1 = Writing a 1 will reset the memory and core graphics clock dividers in the FSB FPLL. This will
Graphics/Memory Clock Gate (GMCLKGATE)—R/W.
0 = Writing a 0 restarts (enable) the clocks.
1 = Writing a 1 cleanly disables the graphics and memory clocks while still enabling the core
NOTE: This bit should always be written to before writing to the FPLLSYNC bit.
DDR interface from the DLL outputs.
graphics logic to come out of reset. After a 1 has been written, the GMCH will take the internal
graphics logic out of reset. From then on, the internal graphics can only be put back into reset
with a hardware reset.
this bit will propagate the IGDIS register to the chip which will make the configuration space
for Device 1 (AGP Bridge) disappear and Device 2 (integrated graphics) appear. Propagating
the IGE will also enable the graphics clock.
core clocks to the processor clock.
also enable the output of the system memory frequency bits and the Graphics Clock Test
Mode register to propagate to the chip and the FPLL.
clocks. The memory and graphics clocks can then be programmed with new speed
information.
60h
00h
R/W, RO
8 bits
Descriptions
Intel
®
82865G/82865GV GMCH Datasheet