21143TD Intel, 21143TD Datasheet - Page 16

• Manufacturer Part Number: 21143TD
• Manufacturer: Intel

Specifications of 21143TD

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

21143
12
gnt_l
idsel
int_l
iref
irdy_l
mii_clsn/
sym_rxd<4>
mii_crs/sd
mii_dv
mii_mdc
mii_mdio
mii/sym_rclk
mii_rx_err/
sel10_100
Signal
Type
O/D
I/O
I/O
I/O
O
I
I
I
I
I
I
I
Table 4. Functional Description of 21143 Signals (Sheet 3 of 6)
Pin Number
108
118
117
129
134
135
128
127
21
34
15
51
Bus grant asserts to indicate to the 21143 that access to the bus is
granted.
Initialization device select asserts to indicate that the host is issuing a
configuration cycle to the 21143.
Interrupt request asserts when one of the appropriate bits of CSR5
sets and causes an interrupt, provided that the corresponding mask
bit in CSR7 is not asserted. Interrupt request deasserts by writing a 1
into the appropriate CSR5 bit.
If more than one interrupt bit is asserted in CSR5 and the host does
not clear all input bits, the 21143 deasserts int_l for one cycle to
support edge-triggered systems.
Current reference input for the analog phase-locked loop logic.
Initiator ready indicates the bus master’s ability to complete the
current data phase of the transaction.
A data phase is completed on any rising edge of the clock when both
irdy_l and target ready trdy_l are asserted. Wait cycles are inserted
until both irdy_l and trdy_l are asserted together.
When the 21143 is the bus master, it asserts irdy_l during write
operations to indicate that valid data is present on the 32-bit ad lines.
During read operations, the 21143 asserts irdy_l to indicate that it is
ready to accept data.
In MII mode (CSR6<18>=1, CSR6<23>=0), this pin functions as the
collision detect. When the external physical layer protocol (PHY)
device detects a collision, it asserts this pin.
In SYM mode (CSR6<18>=1, CSR6<23>=1), this pin functions as
receive data. This line along with the four receive lines
(sym_rxd<3:0>) provides five parallel data lines in symbol form. This
data is controlled by an external physical layer medium-dependent
(PMD) device and should be synchronized to the sym_rclk signal.
In MII mode this pin functions as the carrier sense and is asserted by
the PHY when the media is active.
In SYM mode this pin functions as the signal detect indication. It is
controlled by an external PMD device.
Data valid is asserted by an external PHY when receive data is
present on the mii_rxd lines and is deasserted at the end of the
packet. This signal should be synchronized with the mii_rclk signal.
MII management data clock is sourced by the 21143 to the PHY
devices as a timing reference for the transfer of information on the
mii_mdio signal.
MII management data input/output transfers control information and
status between the PHY and the 21143.
Supports either the 25-MHz or 2.5-MHz receive clock. This clock is
recovered by the PHY.
When used with an MII PHY device (CSR6<18>=1, CSR6<23>=0),
this pin functions as receive error input. It is asserted when a data
decoding error is detected by an external PHY device. This signal is
synchronized to mii_rclk and can be asserted for a minimum of one
receive clock. When asserted during a packet reception, it sets the
cyclic redundancy check (CRC) error bit in the receive descriptor
(RDES0).
When used with a SYM PHY device (CSR6<23>=1), this pin
functions as select 10/100 output. The signal sel10_100 equals 1
when the 21143 is in 100-Mb/s SYM mode (CSR6<18>=1) and
equals 0 when the 21143 is in 10BASE-T/AUI mode (CSR6<18>=0).
Description
Preliminary
Datasheet