21143TD Intel, 21143TD Datasheet - Page 28

• Manufacturer Part Number: 21143TD
• Manufacturer: Intel

Specifications of 21143TD

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

21143
3.4.4
24
Other PCI and CardBus Signals
Figure 5
lists their timing specifications. This timing is identical to the timing for the general-purpose
register signals.
1.
2.
3.
4.
5.
6.
Tval
Ton
Toff
Tsu
Th
Slewr, Slewf
Slewr, Slewf
Load for this measurement is as specified in PCI Local Bus Specification, Revision 2.0 and PCI Local Bus Specification ,
Revision 2.1.
Valid delays for PCI, selected by default when pin cb_pad_l is not pulled down externally.
Valid delays for CardBus, selected by default when pin cb_pad_l is pulled down externally.
Parameter design guarantee.
Slew rate for PCI, selected by default when pin cb_pad_l is not pulled down externally.
Slew rate for CardBus, selected when pin cb_pad_l is pulled down externally.
4
1
4
1
Symbol
shows the timing diagram characteristics for other PCI and CardBus signals and
Table 18. Other PCI and CardBus Signals’ Timing Specifications
4
4
Input
1
Clk
Output
Vtest is 1.5 V in a 5.0-V signaling environment and is 0.4 * vdd_clamp
in a 3.3-V signaling environment.
Vtest
Figure 5. Timing Diagram for Other PCI and CardBus Signals
clk-to-signal valid delay
Float-to-active delay from clk
Active-to-float delay from clk
Input signal valid setup time before clk
Input signal hold time from clk
Output rise and fall slew rate
Output rise and fall slew rate
1
Ton
Tval (max)
Parameter
2
Tsu
5
6
3
Th
Tval (min)
Toff
Minimum
0.25 V/ns
1 V/ns
2 ns
2 ns
7 ns
0 ns
—
Preliminary
LJ04719A.AI4
Maximum
4 V/ns
1 V/ns
11 ns
28 ns
—
—
—
Datasheet
Table 18