HI-3584PQT-10 Holt Integrated Circuits, HI-3584PQT-10 Datasheet - Page 3

• Manufacturer Part Number: HI-3584PQT-10
• Manufacturer: Holt Integrated Circuits

Specifications of HI-3584PQT-10

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3584 contains a 16-bit control register which is used to con-
figure the device. The control register bits CR0 - CR15 are loaded
from BD00 - BD15 when
ter contents are output on the databus when SEL = 1 and
pulsed low. Each bit of the control register has the following func-
tion:
CR10
CR12
CR13
CR14
CR15
CR11
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR
Bit
Label Memory
Enable Label
Enable Label
FUNCTION
Read / Write
(Receiver 1)
(Receiver 2)
Recognition
Recognition
Transmitter
Transmitter
Receiver 1
Receiver 1
Receiver 2
Receiver 2
Data clock
data clock
data clock
as parity
Self Test
Decoder
32nd bit
decoder
Enable
format
Select
Invert
select
select
parity
Data
-
-
-
-
CWSTR
STATE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
-
-
-
is pulsed low. The control regis-
the ARINC bit 10 must match this bit
the ARINC bit 10 must match this bit
Data rate=CLK/10, O/P slope=1.5us
Data rate=CLK/80, O/P slope=10us
the ARINC bit 9 must match this bit
the ARINC bit 9 must match this bit
Transmitter 32nd bit is Even parity
Transmitter 32nd bit is Odd parity
ARINC bits 9 and 10 must match
ARINC bits 9 and 10 must match
Read 16 labels using
outputs are internally connected
If receiver 1 decoder is enabled,
If receiver 1 decoder is enabled,
If receiver 2 decoder is enabled,
If receiver 2 decoder is enabled,
Load 16 labels using
The 429DO and
Transmitter 32nd bit is parity
Receiver 1 decoder disabled
Receiver 2 decoder disabled
Transmitter 32nd bit is data
Disable Label Recognition
to the receiver logic inputs
Enable Label recognition
Disable label recognition
Unscramble ARINC data
Enable label recognition
Scramble ARINC data
Data rate = CLK/10
Data rate = CLK/80
Data rate=CLK/10
Data rate=CLK/80
DESCRIPTION
Normal operation
Normal operation
CR10 and CR11
CR7 and CR8
HOLT INTEGRATED CIRCUITS
429DO
EN1 EN2
PL1 PL2
digital
/
/
RSR
HI-3584
is
3
STATUS REGISTER
The HI-3584 contains a 9-bit status register which can be interro-
gated to determine the status of the ARINC receivers, data FIFOs
and transmitter. The contents of the status register are output on
BD00 - BD08 when the
bits are output as zeros. The following table defines the status reg-
ister bits.
SR1
SR2
SR3
SR4
SR5
SR6
SR7
SR8
SR0
SR
Bit
Transmitter FIFO
Transmitter FIFO
Transmitter FIFO
FUNCTION
FIFO half full
FIFO half full
(Receiver 1)
(Receiver 1)
(Receiver 1)
(Receiver 2)
(Receiver 2)
(Receiver 2)
Data ready
Data ready
FIFO full
FIFO full
half full
empty
full
RSR
STATE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
pin is taken low and SEL = 0. Unused
Receiver 1 FIFO empty
Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read.
this bit
Receiver 1 FIFO holds less than 16
words
Receiver 1 FIFO holds at least 16
words.
this bit.
Receiver 1 FIFO not full
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period.
the inverse of this bit
Receiver 2 FIFO empty
Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read.
this bit
Receiver 2 FIFO holds less than 16
words
Receiver 2 FIFO holds at least 16
words.
this bit.
Receiver 2 FIFO not full
Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period.
the inverse of this bit
Transmitter FIFO not empty
Transmitter FIFO empty.
Transmitter FIFO not full
Transmitter FIFO full.
inverse of this bit.
Transmitter FIFO contains less than
16 words
Transmitter FIFO contains at least
16 words.
inverse of this bit.
HF1
HF2
DESCRIPTION
HFT
D/R1
D/R2
pin is the inverse of
pin is the inverse of
pin is the
pin is the inverse of
pin is the inverse of
FFT
FF1
FF2
pin is the
pin is
pin is