PEB20571FV3.1XT Infineon Technologies, PEB20571FV3.1XT Datasheet - Page 114
PEB20571FV3.1XT
Manufacturer Part Number
PEB20571FV3.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB20571FV3.1XT.pdf
(308 pages)
Specifications of PEB20571FV3.1XT
Lead Free Status / Rohs Status
Compliant
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Table 31
Data-Rate
Mode
2 x 32
time slots/frame
1 x 6
time slots/frame
1 x 12
time slots/frame
1 x 64
time slots/frame
Table 30
Data Rate
2 x 2.048 Mbit/s
1 x 384 kbit/s
1 x 768 kbit/s
1 x 4.096 Mbit/s
4.3.2.3
The D-buffer is mapped to a fixed DSP address space. Every DSP access to the D-buffer
space is directed automatically to the appropriate sub-buffer. E.g. the address of time
slot 5 is 0x8005 in receive and 0x8045 in transmit direction.
.
Data Sheet
DSP Access to the D-Buffer
D-Buffer Address Space
I-Buffer Logical Memory Mapping
00
00
00
00
8000
8000
8000
8000
801F
800B
803F
8005
H
H
H
H
in0
in0
- 0B
- 1F
- 05
- 3F
H
H
H
H
Input Blocks
H
H
H
H
H
H
H
H
-
-
-
-
20
8020
803F
H
in1
in1
97
--
--
--
- 3F
-
-
-
H
H
H
-
D-Buffer
40
40
40
40
8040
8040
8040
8040
804B
805F
8045
807F
H
H
H
H
out0
out0
- 5F
- 4B
- 7F
- 05
Output Blocks
H
H
H
H
Functional Description
H
H
H
H
H
-
-
-
-
H
H
H
60
PEB 20570
PEB 20571
8060
807F
H
out1
out1
2003-07-31
--
--
--
- 7F
-
-
-
H
H
-
H
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