PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 146

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1)
4.5.8
MASKS
Value after reset: FF
Bit 3..0
4.5.9
S_ MODE
Value after reset: 02
Data Sheet
Register SQRR stays valid as long as no code change has been received.
7
1
7
0
MASKS - Mask S-Transceiver Interrupt
S_MODE - S-Transceiver Mode
0 =
1 =
Mask bits
0 =
1 =
The transceiver interrupts LD, RIC, SQC and SQW are enabled
The transceiver interrupts LD, RIC, SQC and SQW are masked
1
0
inactive
The S channel data for the next multiframe is writable.
The register for the S bits to be transmitted has to be written within
the next multiframe. This bit is reset by writing register SQXR.
This timing signal is indicated with the start of every multiframe.
Data which is written right after SQW-indication will be transmitted
with the start of the following multiframe. Data which is written
before SQW-indication is transmitted in the multiframe which is
indicated by SQW.
SQW and SQC could be generated at the same time.
H
H
1
0
1
0
read/write
read/write
134
DCH_INH
LD
RIC
Register Description
MODE
Address:
SQC
Address:
PEF 82902
2001-11-09
SQW
0
0
3A
39
H
H