PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 160

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

TSS
4.7.9
IOM_CR
Value after reset: 08
SPU
TIC_DIS
EN_BCL
DIS_OD
Data Sheet
SPU
7
IOM_CR - Control Register IOM Data
Timeslot Selection
Selects one of 12 timeslots on the IOM
during which SDS2 is active high. The data strobe signal allows standard
data devices to access a programmable channel.
Software Power UP
0 =
1 =
TIC Bus Disable
0 =
1 =
Enable Bit Clock BCL
0 =
1 =
Disable Open Drain
0 =
1 =
0
The DU line is normally used for transmitting data.
Setting this bit to ‘1’ will pull the DU line to low. This will enforce the
T-SMINT
clocking.
The last octet of the last IOM time slot (TS 11) is used as TIC bus.
The TIC bus is disabled. The last octet of the last IOM time slot
(TS 11) can be used like any other time slot. This means that the
timeslots TIC, A/B, S/G and BAC are not available any more.
The BCL clock is disabled (output is high impedant)
The BCL clock is enabled
IOM outputs are open drain driver
IOM outputs are push pull driver
H
â
0
I and other connected layer 1 devices to deliver IOM-
TIC_DIS EN_BCL
read/write
148
®
-2 interface (with respect to FSC)
0
Register Description
DIS_OD DIS_IOM
Address:
PEF 82902
2001-11-09
0
56
H