PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 101

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

Figure 26
In LT-T configurations, the DELIC receives the reference clock from the Central Office
via the IOM-2000 REFCLK line. The VIP selects the reference clock source via two
multiplexers. The source may be either one of the 8 VIP channels operated in LT-T mode
or the CLKIN pin when driving multiple cascaded VIPs on the IOM-2000.
Data Sheet
– F
– L.
– D
– E
– F
– N
– B1
– B2
– A
– S
– M
A
Framing Bit
D.C. Balancing Bit
D-Channel Data Bit
D-Channel Echo Bit
Auxiliary Framing Bit
B1-Channel Data Bit
B2-Channel Data Bit
Activation Bit
S-Channel Data Bit
Multiframing Bit
Frame Structure at Reference Points S and T (ITU I.430)
F = (0b)
frame (always positive pulse)
L. = (0b)
after the last L. bit was odd
signaling data specified by user
E = D if D-channel is not blocked, otherwise
E = D. (ZEROs always overwrite ONEs
See section 6.3 in ITU I.430
N =
User data
User data
A = (0b)
A = (1b)
S
M = (1b)
84
1
or S
F
A
2
channel data
code violation, identifies a new
INFO 2 transmitted
INFO 4 transmitted
number of binary ZEROs sent
Start of new multi-frame
Functional Description
PEB 20570
PEB 20571
2003-07-31