PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 221

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

6.2.6.7
GMOD Register 0
GMOD Register 1
GMOD Register 2
GMOD Register 3
Reset value: 0140
CRCMOD
(1:0)
OPMOD(1:0) Operational Mode
IFTF
Data Sheet
CLASS
15
7
x
GHDLC Mode Registers
CRC Mode
00 =
01 =
10 =
11 =
Programs the mode of the GHDLC channel
Note: Every channel of GHDLC, that is not in use, should be
00 =
01 =
10 =
11 =
Interframe Time Fill
0 =
COLLD
H
14
x
6
programmed to Async mode (OPMOD = "10"), in order to prevent
any access of the idled channels to the GHDLC buffers. For
example, if GHDLC channel mode register CHMOD = "00"
(operation only of channel 0) then OPMOD field in registers GMOD
1/2/3 should be set to "10" (Async mode)
CRC algorithm disabled
16-bit CRC algorithm
32-bit CRC algorithm
reserved
HDLC mode
Extended transparent mode
Asynchronous mode (enables accesses to register GASYNC)
reserved
Sequence of ’1s’ is used as interframe time fill characters
(X
PPOD
31
13
5
+X
x
26
+X
23
+X
IFTF
12
22
read/write
read/write
read/write
read/write
4
x
+X
204
(X
16
+X
16
+X
12
GEM
+X
12
OPMOD(1:0)
11
+X
3
11
+X
5
+1)
10
+X
GEDGE
8
+X
10
2
7
+X
5
Register Description
+X
4
+X
EDGE
Address: D0C6
Address: D0C7
Address: D0C8
Address: D0C9
CRCMOD(1:0)
2
9
1
+X
1
PEB 20570
PEB 20571
+1)
2003-07-31
TE
8
0
H
H
H
H