PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 133

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

4.6.2.3
When placing the last octet of the message into the Transmit Input Buffer, the DSP
places an End transmission command in place of the Start transmission command
without changing the CRC bit.
If CRC encoding is required, the CRC vector will be transmitted bit by bit after the octet
of the message, and then a flag will be transmitted. If CRC encoding is not required, a
flag will be transmitted directly after the last octet of the message.
4.6.2.4
In order to abort transmission of a message over a dedicated channel, the DSP places
an abort command in the appropriate address in the command RAM. The message
being transmitted over the channel is aborted and ’ones’ are transmitted over the
channel instead (even in shared flag mode).
4.6.2.5
Reading a channel from the Receive Output Buffer and writing to a channel in the
Transmit Input Buffer is done according to the channel status vector and according to the
Empty and Full procedures as shown below:
Empty procedure
• If the EMPTY flag of a channel is set by the HDLCU to ‘1’, then move a new time slot
• If the pipe is empty change the pipe page and ask for the next 8 bytes of data from the
Note: The B-channel buffer may be emptied within a single frame, while it takes at least
Full procedure
• If the FULL flag of a channel is set by the HDLCU to ‘1’ then the DSP moves the time
• If the pipe is full change the pipe page and transfer the next 8 bytes of data to the
Note: The B-channel buffer may be filled within a single frame, while a D-channel buffer
4.6.3
The multichannel HDLC controller can be assigned to any timeslot on any time-division
multiplexing (TDM) port: IOM-2, PCM and TRANSIU.
Data Sheet
to be transmitted from the pipe to the Transmit Input Buffer.
external controller by means of DMA or transfer ready indication.
slot from the Receive Output Buffer into the double buffer.
External Controller by means of DMA or transfer ready indication.
4 frames to empty a D-channel buffer.
will take at least 4 frames to fill.
Ending a Transmission
Aborting a Transmission
DSP Access to the HDLCU Buffers
Functionality
116
Functional Description
PEB 20570
PEB 20571
2003-07-31