IXP2400 Intel, IXP2400 Datasheet - Page 20

• Manufacturer Part Number: IXP2400
• Manufacturer: Intel

Specifications of IXP2400

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel
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IXP2400 Network Processor
Note: SPI3 is the name associated with POS-PHY Level 3.
In UTOPIA and POS-PHY modes, each port can function as a single 32-bit interface, or can be
subdivided into a combination of 8- or 16-bit channels. Each channel is a point-to-point connection
to a single physical layer device. Each Channel operates independently when subdivided. In
addition to single-PHY mode, the IXP2400 supports multi-PHY (MPHY) mode. In MPHY mode,
the 32-bit bus is shared by up to 16 ports in accordance with the UTOPIA Level 3 and POS PHY
Level 3 Specifications. Master Mode only is supported in UTOPIA and POS-PHY modes.
The Optical Inter-networking Forum (OIF) controls the SPI3 Implementation Agreement
document (available at http://www.oiforum.com).
CSIX
The IXP2400 implements CSIX_L1 (Common Switch Interface) for signalling and clocks.
CSIX_L1 defines an interface between a Traffic Manager (TM) and a Switch Fabric (SF) for ATM,
IP, MPLS, Ethernet, and similar data communications applications. The basic unit of information
transferred between TMs and SFs is called a CFrame. There are a number of CFrame types defined,
but they can be basically categorized as either Data, Control, or Flow Control. Associated with
each CFrame is information such as length, type, address. This information is collected by the MSF
and passed to Microengines.
The Network Processor Forum (NPF) controls the CSIX_L1 specification (available at
http://www.npforum.org).
PCI Controller
The PCI Controller provides 64-bit, 66-MHz-capable PCI Rev. 2.2 interface. It is also compatible
to 32-bit and/or 33-MHz PCI devices. The PCI controller provides the following functions:
The IXP2400 can be configured to act as PCI central function, or can own the arbitration.
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A Flow Control Interface, which provides a point-to-point connection used to pass CSIX-L1-B
flow control C-Frames either between two IXP2400 network processors or between a IXP2400
and a CSIX-L1-B switch fabric.
Each 32-bit interface can be subdivided into 8- or 16-bit channel combinations. The MSF
interface uses 3.3V LVTTL (low-voltage transistor-transistor logic) signaling. While the
CSIX standard is a source-synchronous bus, the IXP2400 uses a common-clocking scheme for
compatibility with the other protocols.
Target access (external bus master access to SRAM, DRAM, and CSRs)
Master access (Intel XScale core or Microengine access to PCI target devices)
Three DMA channels
Mailbox and Doorbell Registers for Intel XScale core-to-host communication
PCI arbiter
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