IXP2400 Intel, IXP2400 Datasheet - Page 63

• Manufacturer Part Number: IXP2400
• Manufacturer: Intel

Specifications of IXP2400

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

3.2.4
Datasheet
Table 23. PCI Signals
PCI
PCI Bus can be used to interface to industry-standard IO devices, or to a host processor. See
23
Total (per channel)
for a list of signals. PCI signaling levels are defined in PCI Rev. 2.2 specification.
PCI_CBE_L[7:0]
PCI_DEVSEL_L
PCI_FRAME_L
PCI_REQ_L[0]
PCI_REQ_L[1]
PCI_GNT_L[0]
PCI_GNT_L[1]
PCI_REQ64_L
PCI_ACK64_L
PCI_AD[63:0]
PCI_PERR_L
PCI_SERR_L
Signal Name
PCI_STOP_L
PCI_TRDY_L
PCI_RCOMP
PCI_IRDY_L
PCI_INTA_L
PCI_INTB_L
PCI_RST_L
PCI_PAR64
PCI_IDSEL
PCI_CLK
PCI_PAR
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
I
I
I
I
I
Clock input for the PCI core clock domain (0 to 66 MHz)
Multiplexed address/data bus
Command and byte enable bus
Active-low PCI reset signal. This is an output if IXP2400 is
the bus host.
It is an input if IXP2400 is not the bus host.
The direction of this pin is controlled by the CFG_RSTDIR
pin.
Receives interrupt from another PCI device if the IXP2400
is the bus host; otherwise used as an interrupt to the host
processor.
Receives interrupt from another PCI device if the IXP2400
is the bus host.
Transaction in progress indication
Termination with retry or disconnect-with-data
Initiator ready on data phase
Target ready on data phase
Device select indication
IdSel signal to the IXP2400; used during the configuration
cycle
Bus requests from external master 0, used when the
IXP2400 is arbiter/host; the IXP2400’s request output to
external arbiter when not a host.
Bus requests from external master 1, used when the
IXP2400 is arbiter/host.
Bus grant output to external master 0 when this chip is
arbiter/host; grant input to the IXP2400 from external arbiter
when not a host.
Bus grants to external master 1, used when the IXP2400 is
arbiter/host
Indication that a 64-bit data phase is desired. During reset,
driven low by the system to indicate 64-bit capability.
Indicates that a 64-bit data phase is accepted.
Parity on AD[31:0]
Parity on AD[63:32]
Parity error detected on incoming data
Parity error on address phase, illegal command, etc. When
this chip is the host SERR is an input; when using with an
external host, SERR is an output.
Buffer Compensation
1
Description
Intel
®
IXP2400 Network Processor
Number
64
93
1
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table
63