IXP2400 Intel, IXP2400 Datasheet - Page 27

• Manufacturer Part Number: IXP2400
• Manufacturer: Intel

Specifications of IXP2400

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

3.2.3.1
Datasheet
Table 6.
MSF Data Signals (Continued)
NOTES:
See
flow control information between two IXP2400 network processors.
MSF Mode Signal Usage
The following tables specify the signal usage for each mode supported by the MSF and the
mapping of these signals to the MSF pinout.
1. The MSF TXRCOMP and RXRCOMP pins should be separately connected to ground through external
2. MSF_CLK_BYPASS is used for debug only. If the MSF PLL fails to work, asserting this signal enables the
RXRCOMP
MSF_CLK_B
YPASS
RSVD[3:0]
Total (per
channel)
1.
2.
3.
4.
5.
6.
7. The pin names assume master mode operation. In slave mode operation, the pins have a
8.
Pin Name
45Ω±1% resistor and one 0603 0.1 µF decoupling capacitor. Place the resistor and capacitor as close to the
IXP2400 as possible, within 1.0” of the package. The compensation signal should be routed with as wide a
trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing.
buffered external clock to bypass the PLL to connect to the internal MSF clock trees. In normal operation, it
should be tied to low.
Table 22 “CBus Pinout” on page 62
Table
these modes, the bus is configured as 1x32, 2x16, 4x8, or 1x16+2x8, and the ports may be any
combination of UTOPIA or POS-PHY SPHY ports, master or slave.
Table 11
Table 12
Table 13
Table 14
SPHY ports. The SPHY ports may be any combination of UTOPIA or POS-PHY, master or
slave.
Table 16
SPHY ports. The SPHY ports may be any combination of UTOPIA or POS-PHY, master or
slave.
different meaning.
slave function mapping for various bus widths.
Table 22
2
7,
1
Table
describes x32 UTOPIA Level 3 MPHY mode pinout.
describes x32 POS-PHY Level 3 MPHY mode pinout.
describes CSIX/CBus mode pinout.
and
and
describes the CBus pinout.
I/O
I
I
Table 15
Table 17
8,
LVTTL
LVTTL
Type
Table
Table
describe x16 UTOPIA Level 2 MPHY mode with one x16 or two x8
describe x16 POS-PHY Level 2 MPHY mode with one x16 or two x8
Receiver compensation
resistor
Media switch fabric PLL
bypass
Reserved pins. These pins
should be No Connect.
9, and
18,
Table
Description
Table 10
19,
for information regarding signals used to communicate
Table
describe the UTOPIA and POS-PHY SPHY modes. In
20, and
Number
142
1
1
4
Table 21
Intel
®
IXP2400 Network Processor
describe the master pin name to
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