CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 18

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

7.3.7
For the search operation where the SSRAM is connected to
the network processor (see Figure 13-1), the Result Register
0 carries the search response (see Table 7-18) and result
register 1 is unused.
Table 7-18. Search Response in Result Register 0 (type I)
Processor ID[4:0]. The processor ID set in the command
descriptor is set here.
Context ID[4:0]. The context ID set in the command
descriptor is set here.
Hit. The hit flag indicates whether the search was successful.
Done. This field indicates that the command has been
processed. The done bit is cleared when the Result Register
0 is Read by the network processor. A new command can be
Table 7-19. Index Bits for NSEs
Note. SAP is the SSRAM Address (SADR) Prefix. These bits
are passed along with the command descriptor word in the
SAP field.
7.3.8
The network processor(s) can Write up to 32 contexts. There
can be up to 32 operations in flight through the database
coprocessing subsystem. If 30 descriptor entries are in use,
the NDC will issue the DESC_AFUL signal to inform that
command descriptor ring is almost full. The database
coprocessor continually executes the commands posted in the
descriptors. The commands are executed and the results
written in the Result Registers 0 and 1 of the corresponding
descriptor entries. The network processor(s) will Read the
results and free the descriptor entry for another command.
The handshake for the command handoff from the network
processor uses the start bit in the command descriptor. The
network processor will load the command and the associative
parameter along with the start bit in the descriptors. As the
start bit in a descriptor is set, the NDC will take the command
and insert it in the pipeline queue for execution. The
commands in the pipeline queue are strictly handled in a first-
in, first-out manner. Note. The network processor must make
Document #: 38-02043 Rev. *C
Bit Positions
63–56
55–48
47–40
39–32
31–24
23–16
15–8
7–0
Result Register 0 and 1 for Search Operation (Case 2)
Functional Overview of Context Descriptor
CYNSE70032
CYNSE70064
CYNSE70128
Device
Done
7
Reserved
Hit
6
Associative Data SSRAM connected to Coprocessor Bus
21:19
21:20
23:21
SAP
Reserved
Reserved
5
4
initiated by the network processor through this descriptor after
the done bit has cleared.
Index. This field contains index returned by the NSEs where
a successful hit was found. This field is valid only if the hit bit
in the Result Register 0 is a 1. Table 7-19 below shows the
number of index bits for various NSEs. Note. CYNSE70032
and CYNSE70064 bits 23–22 of the index will always be 00.
(Refer to the specifications of the CYNSE70XXX for the
description of the index returned by the NSEs.)
sure that the start bit is set in the last access to the descriptor
to complete the command.
The commands from the pipeline queue are continually
executed by the NDC and the results are loaded back to the
command initiating descriptor’s Result Registers 0 and 1. The
handshake for the results from the NDC back to network
processor is done through any of the following mechanisms:
In the first method, after the network processor has issued a
command to the NDC, the network processor will continually
poll that command descriptor entry for the done bit. Once done
bit is set, it signals to the network processor that the results are
Ready in Results Registers 0 and 1 for Readout. Reading of
these registers by the network processor will clear the done
bit. This descriptor entry is free and may now be used for
another command.
In the second method, the network processor uses the
interrupt mechanism for Reading the command results. After
the results are Ready in Result Registers 0 and 1 and the done
bit is set, the NDC will assert pins CPID[7:0] (with the
concatenated processor and context ID information) and
Index [23:16]
Index [15:8]
• Done bit
• CPID bus, STRB signal.
Index [7:0]
Reserved
Reserved
Reserved
18:14
19:15
20:16
SEID
3
Processor ID[4:0]
Context ID [4:0]
2
CYNCP80192
Index
1
13:0
14:0
15:0
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