DAC1205D650HW/C1,5 NXP Semiconductors, DAC1205D650HW/C1,5 Datasheet - Page 14

• Manufacturer Part Number: DAC1205D650HW/C1,5
• Description: IC DAC 12BIT 650MSPS DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1205D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 12
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286777518

NXP Semiconductors
DAC1205D650
Product data sheet
Fig 3.
RESET_N
(optional)
SCS_N
SCLK
SDIO
SDO
R/W indicates the mode access (see
SPI protocol
10.2.2 SPI timing description
R/W
Table 6.
In
Table 7.
A0 to A4: indicates which register is being addressed. In the case of a multiple transfer,
this address concerns the first register after which the next registers follow directly in
decreasing order according to
The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure
R/W
0
1
N1
0
0
1
1
N1
Fig 4.
Table 7
RESET_N
N0
4.
SCS_N
SCLK
SDIO
SPI timing diagram
N1 and N0 indicate the number of bytes transferred after the instruction byte.
Read or Write mode access description
Number of bytes to be transferred
A4
All information provided in this document is subject to legal disclaimers.
Table
A3
Description
Write mode operation
Read mode operation
50 %
50 %
N0
0
1
0
1
50 %
Rev. 2 — 13 September 2010
6).
A2
t
w(RESET_N)
50 %
Dual 12-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
A1
Table 9 “Register allocation
t
t
su(SCS_N)
su(SDIO)
A0
t
h(SDIO)
D7
D7
Number of bytes
1 byte transferred
2 bytes transferred
3 bytes transferred
4 bytes transferred
D6
D6
D5
D5
t
w(SCLK)
D4
D4
map”.
DAC1205D650
D3
D3
D2
D2
© NXP B.V. 2010. All rights reserved.
D1
D1
D0
D0
t
001aaj813
h(SCS_N)
001aaj812
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