DAC1205D650HW/C1,5 NXP Semiconductors, DAC1205D650HW/C1,5 Datasheet - Page 22

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DAC1205D650HW/C1,5

Manufacturer Part Number
DAC1205D650HW/C1,5
Description
IC DAC 12BIT 650MSPS DL 100HTQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of DAC1205D650HW/C1,5

Settling Time
20ns
Number Of Bits
12
Data Interface
SPI™
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
1.4W
Operating Temperature
-45°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935286777518

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DAC1205D650HW/C1,5
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NXP Semiconductors
DAC1205D650
Product data sheet
In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, depending on the SELIQ signal; see
The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and
Q channels; see
edge)”.
SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse)
signal. The first data bits following the SELIQ rising edge are sent in channel I and
following data bits are sent in channel Q. After this, the data is distributed alternately
between both channels.
Fig 6.
Fig 7.
(asynchronous alternative 1)
(asynchronous alternative 2)
n in Qn = 11 and for In is 0 to 11.
Interleaved mode operation
Interleaved mode timing (8× interpolation, latch on rising edge)
(synchronous alternative)
Qn/SELIQ
All information provided in this document is subject to legal disclaimers.
In
Figure 7 “Interleaved mode timing (8¥ interpolation, latch on rising
Latch Q output
Latch I output
Rev. 2 — 13 September 2010
CLK
SELIQ
SELIQ
SELIQ
Dual 12-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
dig
In
LATCH
LATCH
Q
I
N
N + 1
2 ×
2 ×
XX
XX
FIR 1
FIR 1
N + 2
2 ×
2 ×
FIR 2
FIR 2
N + 3
N + 1
N
DAC1205D650
N + 4
Figure
2 ×
2 ×
FIR 3
FIR 3
© NXP B.V. 2010. All rights reserved.
N + 5
N + 2
N + 3
001aaj586
001aaj814
7.
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