AD5532ABC-3 Analog Devices Inc, AD5532ABC-3 Datasheet - Page 17

• Manufacturer Part Number: AD5532ABC-3
• Description: IC DAC 14BIT 32CH 74-CSPBGA
• Manufacturer: Analog Devices Inc

Specifications of AD5532ABC-3

• Rohs Status: RoHS non-compliant
• Settling Time: 22µs
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 34
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 623mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 74-CSPBGA
• For Use With: EVAL-AD5532HSEBZ - BOARD EVAL FOR AD5532HSEVAL-AD5532EBZ - BOARD EVAL FOR AD5532

PARALLEL INTERFACE (ISHA MODE ONLY)
The SER/ PAR bit must be tied low to enable the parallel
interface and disable the serial interface. The parallel interface is
controlled by nine pins, as described in
Table 11.
Pin
CS
WR
A4–A0
OFFSET_SEL
CAL
MICROPROCESSOR INTERFACING
AD5532 to ADSP-21xx Interface
ADSP-21xx DSPs are easily interfaced to the AD5532 without
the need for extra logic.
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP serial clock and
clocked into the AD5532 on the falling edge of its SCLK. In
readback, 16 bits of data are clocked out of the AD5532 on each
rising edge of SCLK and clocked into the DSP on the rising
edge of SCLK. D
centered in the 16-bit RX register in this configuration. The
SPORT Control register should be set up as in Table 12.
Table 12.
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
SLEN = 1001
SLEN = 0111
SLEN = 1111
Description
Active low package select pin. This pin is shared
with the SYNC function for the serial interface.
Active low write pin. The values on the address
pins are latched on a rising edge of WR.
Five address pins (A4 = MSB of address,
A0 = LSB). These are used to address the
relevant channel (out of a possible 32).
Offset select pin. This has the same function as
the Offset_Sel bit in the serial interface. When it
is high, the offset channel is addressed. The
address on A4–A0 is ignored in this case.
When this pin is high, all 32 channels acquire
VIN simultaneously. The acquisition time is then
45 μs (typ) and accuracy may be reduced.
IN
is ignored. The valid 14 bits of data is
Alternate framing
Active low frame signal
Right justify data
Internal serial clock
Frame every word
External framing signal
Internal framing signal
10-bit data-words (ISHA mode write)
3 × 8-bit data-words (DAC mode write)
16-bit data-words (Readback mode)
Table 11
.
Rev. D | Page 17 of 20
Figure 22 shows the connection diagram.
AD5532 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual . SCK of the 68HC11 drives the SCLK
of the AD5532, the MOSI output drives the serial data line (D
of the AD5532, and the MISO input is driven from D
SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5532, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To transmit
10 data bits in ISHA mode, it is important to left-justify the data
in the SPDR register. PC7 must be pulled low to start a transfer.
It is taken high and pulled low again before other read/write
cycles can take place.
Figure 22. AD5532 to ADSP-2101/ADSP-2103 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5532*
AD5532*
Figure 23. AD5532 to MC68HC11 Interface
SYNC
SYNC
SCLK
SCLK
D
D
Figure 23
OUT
OUT
D
D
IN
IN
shows a connection diagram.
DR
TFS
RFS
DT
SCLK
MISO
PC7
SCK
MOSI
ADSP-2103*
ADSP-2101/
MC68HC11*
AD5532
OUT
. The
IN
)