82V1068PF8 IDT, Integrated Device Technology Inc, 82V1068PF8 Datasheet - Page 25

• Manufacturer Part Number: 82V1068PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1068PF8

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.6V
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC
3
3.1
control interface (MPI mode) or via the GCI monitor channel (GCI
mode). In both MPI and GCI modes, the programming is realized by
writing commands to registers or RAMs on the chip. In MPI mode, the
command data is transmitted/received via the CI/CO pin. In GCI mode,
the command data is sent/received via the DD/DU pin.
3.1.1
in read operation). Each channel has its own enable bit (CE[0] to CE[7]
in Global Register 6) to allow individual channel programming. If more
than one Channel Enable bit is high (enable) or all Channel Enable bits
are high, all the corresponding channels will be enabled and can receive
the programming information. Therefore, a broadcasting mode can be
implemented by simply enabling all the channels in the device to receive
the programming information. The Broadcasting mode is very useful
when initializing the IDT82V1068 (setting coefficients, for example) in a
large system.
3.1.2
distinguish itself from other device of the system. When being read, the
IDT82V1068 first outputs an Identification Code of 81H to indicate that
the following data is from the IDT82V1068, then outputs the data bytes.
Refer to
3.1.3
mode information with the high level processors. The messages
transmitted in the monitor channel have different data structures. For a
complete command operation, the first byte of monitor channel data
indicates the address of the device either sending or receiving the data.
All monitor channel messages to/from the IDT82V1068 begin with the
following Program Start (PS) byte:
the A/B bit is necessary to be used in the PS byte to identify the two
channels (named as Channel A and Channel B).
destination (downstream) -81H;
destination (downstream) -91H.
command or RAM command) byte. For Global Commands, the A/B bit in
the PS byte will be ignored. If the command byte specifies a write, there
may be 1 to 16 additional data bytes follows (1-4 bytes for registers, 1-
16 bytes for RAM). If the command byte specifies a read, additional data
bytes may follow. The IDT82V1068 responds to the read command by
sending up to 16 data bytes upstream containing the information
The IDT82V1068 can be programmed very flexibly via the serial
A broadcasting mode is provided in MPI write-operation (not allowed
In MPI mode, the IDT82V1068 provides an Identification Code to
The IDT82V1068 uses the monitor channel to exchange the status or
Because one monitor channel is shared by two voice data channels,
A/B = 0: means that Channel A is the source (upstream) or
A/B = 1: means that Channel B is the source (upstream) or
The Program Start byte is followed by a command (global/local
b7
1
Table 5
b6
0
OPERATING DESCRIPTION
PROGRAMMING DESCRIPTION
BROADCASTING MODE FOR MPI PROGRAMMING
IDENTIFICATION CODE FOR MPI MODE
PROGRAM START BYTE FOR GCI MODE
and
Table 6 on page 27
b5
0
A/B
b4
b3
0
for details.
b2
0
b1
0
b0
1
25
requested by the upstream controller. Each byte on monitor channel
must be transferred at least twice and in two consecutive frames.
3.1.4
two byte identification command (8000H) is defined for analog lines GCI
devices:
the IDT82V1068, this two byte identification code is 8082H:
3.1.5
for both MPI and GCI modes, they are:
are 12 Local Registers per channel.
are total 26 Global Registers shared by all eight channels.
RAM. There are 40 words (divided into 5 blocks) Coe-RAM for each
channel, each word has 14 valid bits. The IDT82V1068 provides four
FSK generators shared by all eight channels. There are 32 words
(divided into 4 blocks) FSK-RAM for each FSK generator, each word has
16 bits.
used to address the Local Registers or Global Registers.
the FSK RAM is to be addressed:
block in the Coe-RAM. When addressing the FSK-RAM, the b3 bit is
always ‘0’ and the b[2:0] bits are used to specify a block in the FSK-
RAM.
R/W
In order to distinguish different devices unambiguously by software, a
Each device will then respond with its specific identification code. For
The IDT82V1068 provides three types of register/RAM commands
Local Command (LC): used to access the Local Registers. There
Global Command (GC): used to access the Global Registers. There
RAM Command (RC): used to access the Coe-RAM and the FSK-
The format of the commands is as the following:
R/W:
CT:
Address: The b[4:0] bits specify a register(s) or a RAM location(s) to
For both Local Commands and Global Commands, the b[4:0] bits are
For RAM Commands, the b4 bit is used to specify if the Coe-RAM or
b4 = 0: addressing the Coe-RAM
b4 = 1: addressing the FSK-RAM
When addressing the Coe-RAM, the b[3:0] bits are used to specify a
b7
1
0
1
1
b6
0
0
0
0
COMMAND TYPE AND FORMAT
IDENTIFICATION COMMAND FOR GCI MODE
Read/Write Command bit
b7 = 0:
b7 = 1:
Command Type
b6 b5 = 00: Local Command
b6 b5 = 01: Global Command
b6 b5 = 10: Not Allowed
b6 b5 = 11: RAM Command
be addressed.
CT
b5
0
0
0
0
Read Command
Write Command
INDUSTRIAL TEMPERATURE RANGE
b4
0
0
0
0
b3
0
0
0
0
Address
b2
0
0
0
0
b1
0
0
0
1
b0
0
0
0
0