82V1068PF8 IDT, Integrated Device Technology Inc, 82V1068PF8 Datasheet - Page 38

• Manufacturer Part Number: 82V1068PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1068PF8

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.6V
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC
GC26:
FSK_G4 = 1:
The IDT82V1068 provides four FSK generators shared by all eight channels. Before configuring the FSK generator(s) (e.g., setting the
Flag Length/Data Length/Seizure Length/Mark Length, selecting the FSK channel and programming the FSK-RAM), this command must
be used first to specify one or more FSK generators to be configured, the FSK configuration registers and FSK-RAM will then be
accessed accordingly. The FSK Generator 1 (FSK_G1) is selected by default.
Loopback Control and PLL Power Down, Read/Write (3CH/BCH)
The loopback control bits (ALB_DI, DLB_DI, DLB_8k, ALB_8k, DLB_ANA, DLB_64k and ALB_64k) determine the loopback status.
Figure 9 on page 19
ALB_DI = 0:
ALB_DI = 1:
DLB_DI = 0:
DLB_DI = 1:
DLB_8k = 0:
DLB_8k = 1:
ALB_8k = 0:
ALB_8k = 1:
DLB_ANA = 0: The digital loopback via analog interface is disabled (default);
DLB_ANA = 1: The digital loopback via analog interface is enabled.
DLB_64k = 0: The digital loopback via 64 kHz interface is disabled (default);
DLB_64k = 1: The digital loopback via 64 kHz interface is enabled;
ALB_64k = 0:
ALB_64k = 1:
The PLL Power Down Bit (PLLPD) controls the status of the Phase Lock Loop.
PLLPD = 0:
PLLPD = 1:
Command
I/O Data
ALB_64k
FSK generator 4 is selected.
The analog loopback via DX to DR is disabled (default);
The analog loopback via DX to DR is enabled;
The digital loopback via DR to DX is disabled (default);
The digital loopback via DR to DX is enabled;
The digital loopback via 8 kHz interface is disabled (default);
The digital loopback via 8 kHz interface is enabled;
The analog loopback via 8 kHz interface is disabled (default);
The analog loopback via 8 kHz interface is enabled;
The analog loopback via 64 kHz interface is disabled (default);
The analog loopback via 64 kHz interface is enabled;
The device is in normal operation (default);
The Phase Lock Loop is powered down. The device works in Power-Saving mode. All clocks stop running.
R/W
b7
shows all the loopbacks and cutoff in the IDT82V1068.
PLLPD
b6
0
DLB_64k
b5
1
DLB_ANA
38
b4
1
ALB_8k
b3
1
DLB_8k
b2
1
INDUSTRIAL TEMPERATURE RANGE
DLB_DI
b1
0
ALB_DI
b0
0