82V1068PF8 IDT, Integrated Device Technology Inc, 82V1068PF8 Datasheet - Page 29

• Manufacturer Part Number: 82V1068PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1068PF8

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.6V
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC
3.2
below:
3.3
RESET pin to logic low for at least 50 µs or by the GCI/MPI Command,
the device will enter the default state as described below:
To power on the IDT82V1068, users should follow the sequence
1. Apply ground first;
2. Apply VCC, finish signal connections and set the RESET pin to
3. Set the RESET pin to high;
4. Select master clock frequency;
5. Program filter coefficients and other parameters as required.
When the IDT82V1068 is powered on, or reset either by setting the
1. All eight channels are powered down and enter standby mode;
2. All loopbacks and cutoff are disabled;
3. The DX1/DU pin is selected for all channels to transmit data, the
4. The master clock frequency is assumed to be 2.048 MHz;
5. For MPI mode, the transmit and receive time slots are set to 0-7
low, thus the device goes into the default state;
DR1/DD pin is selected for all channels to receive data;
for channel 1-8 respectively. The PCM data rate is as same as
POWER-ON SEQUENCE
DEFAULT STATE AFTER RESET
29
operations. In this way, the RAM data will not be lost unless the device is
powered down physically.
6. A-Law is selected;
7. The coefficients of FRX, FRR, GTX and GTR filters are set to
8. The SB1 and SB2 pins are configured as inputs;
9. The SI1 and SI2 pins are configured as no debounce pins;
10. All interrupts are disabled, all pending interrupts are cleared;
11. All feature function blocks including FSK generators, dual tone
12. The CHCLK1 and CHCLK2 outputs are set to high.
The data stored in the RAMs will not be changed by any kind of reset
the BCLK frequency. Data is transmitted on the rising edges and
received on the falling edges of the BCLK signal;
For GCI mode, the time slots for transmitting and receiving are
determined by the TS pin. the data rate is determined by the
DOUBLE pin. The DD/DU clocks data on the rising edges of the
DCL signal.
default values. The analog gains are set to 0 dB. The IMF, GIS
and ECF filters are disabled. The HPF filter is enabled (Refer to
Figure 9
generators, ring trip and level metering are turned off;
for more information about the filters);
INDUSTRIAL TEMPERATURE RANGE