PF38F5060M0Y0CFB Micron Technology Inc, PF38F5060M0Y0CFB Datasheet - Page 78
PF38F5060M0Y0CFB
Manufacturer Part Number
PF38F5060M0Y0CFB
Description
Manufacturer
Micron Technology Inc
Datasheet
1.PF38F5060M0Y0CFB.pdf
(102 pages)
Specifications of PF38F5060M0Y0CFB
Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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14.0
Table 30: Read Configuration Register Summary
Table 31: Read Configuration Register Descriptions (Sheet 1 of 2)
Datasheet
78
RM
15
13-11
Bit
15
14
10
9
8
7
6
5
4
14
R
First Access Latency
LC2
First Access Latency Count
Data Output Configuration
Set Read Configuration Register
The Set Read Configuration Register (RCR) command sets the burst order, frequency
configuration, burst length, and other parameters.
A two-bus cycle command sequence initiates this operation. The Read Configuration
Register data is placed on the lower 16 bits of the address bus (A[15:0]) during both
bus cycles. The Set Read Configuration Register command is written along with the
configuration data (on the address bus). This is followed by a second write that
confirms the operation and again presents the Read Configuration Register data on the
address bus. The Read Configuration Register data is latched on the rising edge of
ADV#, CE#, or WE# (whichever occurs first). This command functions independently of
the applied V
mode. The Read Configuration Register’s contents can be examined by writing the Read
Identifier command and then reading location 05h. See
13
WC WAIT Configuration
WAIT Signal Polarity
Clock Configuration
Burst Sequence
Count
Read Mode
LC1
12
LC[2:0]
Name
DOC
RM
WT
BS
CC
R
R
R
LC0
PP
11
voltage. After executing this command, the device returns to read-array
WT
10
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
Reserved
001 = Reserved
010 = Code 2
011 = Code 3
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
1 = Linear Burst Order (Default)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
Reserved
Reserved
DOC
9
WC
8
BS
7
Description
CC
6
100 = Code 4
101 = Code 5
111 = Reserved (Default)
Numonyx™ Wireless Flash Memory (W18)
Numonyx™ Wireless Flash Memory (W18)
R
5
1
Table 30
R
4
BW
and
3
Order Number: 290701-18
Table
BL2
2
Burst Length
November 2007
31.
BL1
1
Notes
2
5
6
3
6
6
5
5
BL0
0
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