ED DDR3 1G PCH9000 Samsung Semiconductor, ED DDR3 1G PCH9000 Datasheet - Page 19

• Manufacturer Part Number: ED DDR3 1G PCH9000
• Manufacturer: Samsung Semiconductor
• Type: DDR3 SDRAMr

Specifications of ED DDR3 1G PCH9000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 20ns
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 160mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

K4B1G04(08/16)46E
9.0 AC & DC Output Measurement Levels
9.1 Single-ended AC & DC Output Levels
[ Table 14 ] Single-ended AC & DC output levels
Note : 1. The swing of +/-0.1 x V
9.2 Differential AC & DC Output Levels
[ Table 15 ] Differential AC & DC output levels
Note : 1. The swing of +/-0.2xV
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
for single ended signals as shown in Table 16 and figure 6.
[ Table 16 ] Single-ended output slew rate definition
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 17 ] Single-ended output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
se : Singe-ended Signals
For Ron = RZQ/7 setting
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
Single ended output slew rate
V
V
V
V
V
V
V
Symbol
OHdiff
Symbol
OLdiff
OH
OM
and an effective test load of 25
and an effective test load of 25
OL
OH
OL
(DC)
(AC)
(DC)
(AC)
(DC)
(DC)
Parameter
(AC)
Parameter
AC differential output high measurement level (for output SR)
AC differential output low measurement level (for output SR)
Parameter
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output SR)
AC output low measurement level (for output SR)
Description
DDQ
DDQ
Symbol
SRQse
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40
Ω
Ω
to V
to V
TT
TT
=V
=V
Figure 6. Single-ended Output Slew Rate Definition
Min
2.5
DDQ
DDQ
DDR3-800
delta
/2.
/2 at each of the differential outputs.
TFse
V
V
Max
OH
From
OL
5
(AC)
(AC)
Page 19 of 61
Measured
Min
2.5
DDR3-1066
V
V
OH
OL
To
(AC)
(AC)
delta
Max
5
TRse
DDR3-800/1066/1333/1600
DDR3-800/1066/1333/1600
Min
2.5
DDR3-1333
V
V
V
OH(AC)
V
TT
OL(AC)
V
TT
TT
+0.2 x V
-0.2 x V
0.8 x V
0.5 x V
0.2 x V
+ 0.1 x V
- 0.1 x V
Max
5
DDQ
DDQ
DDQ
DDQ
DDQ
1Gb DDR3 SDRAM
DDQ
V
V
DDQ
OH
OH
Defined by
Delta TRse
Rev. 1.0 February 2009
Delta TFse
(AC)-V
(AC)-V
TBD
Min
DDR3-1600
OL
OL
(AC)
(AC)
OL
Max
Units
Units
5
(AC) and V
V
V
V
V
V
V
V
Units
Notes
Notes
V/ns
OH
1
1
1
1
(AC)
Ω
Ω